Moderator summary (Kevin Skadron)
In an era of multicore chips, power and temperature become even more
important determinants of an optimal design. To focus our discussion
in the short time available, we have agreed on a short list of topics
that we think will generate vigorous discussion:
- How important is explicit hotspot management in a multicore era, versus
generally minimizing overall power dissipation?
- What is the importance of techniques explicitly focused on leakage
- How should we evaluate power and thermal management in multicore
chips? Detailed simulation or analytical models?
- Do we need dedicated controller cores for power/thermal management?
Panelist Kanad Ghose
Multicore processors are here to stay.
- Architects need to focus on addressing power in the on-chip
memory hierarchy of multicore designs very explicitly.
- Looking at just peak temperatures/peak power to throttle down
activities is useless: limiting average temperature and average power
dissipation is just as important.
- Without accurate, integrated tools for studying power, performance
tradeoffs for multicore systems, not much progress can be made.
- Just designing a general-purpose energy-efficient processor is not
enough: the focus should shift from designing energy-efficient
processors to energy-efficient systems - a holistic approach that
includes OSs, libraries, protocol stacks and compilers.
Microarchitects should design simple energy/performance management
hooks in the processor and all other components (RAMs, controllers,
chipsets, interconnections) that can be exposed to the software, going
beyond voltage/clock scaling. Subsystems need to have
power-performance gears to support power management at a higher level.
We cannot pull this off by just gating and controlling cores.
Inherently low-power components do not need to have adaptive
management - global energy management is critical.
Panelist Pradip Bose
I personally find the following topics to be key for architects:
- Microarchitecture research should emphasize mitigation of thermal
hotspots (high power density regions). We need an increased focus on
distributing power more evenly across the chip, to reduce peak power
density and temperature. Proposing inherently power-efficient
(micro) architectures and functional units should should come
first, before before considering additional leverage from dynamic
reconfiguration of structures (esp. low power density structures).
At runtime, dynamic task distribution is effective - and we should
pursue integrated (hardware/software) solutions to exploit this.
- Throttling on temperature threshold is just a "damage control"
emergency measure, not for routine use. Smarter methods for achieving
power (re)distribution in order to routinely manage and mitigate hot
spots is the right approach.
- We need a renewed emphasis on "fundamental understanding"
models: analytic or hybrid to better guide the chip-level microarchitect. I will argue that this is more urgent and useful then
developing either detailed full-system simulators or FPGA-based
- Process variability and noise will make statically efficient,
reliable designs much harder. On-chip sensors, sensor networks,
monitoring and control of resources for "optimal" management of power,
temperature, reliability, performance create a multi-dimensional
control/optimization problem that will inevitably point to the need
for dedicated on-chip, programmable controller(s). This presents many
open research problems and issues in ensuring control stability,
handling of increasing levels of on-chip asynchrony, etc. Verification
challenges will continue to pose as the greatest obstacle to such
microarchitectural trends - but modular design principles will
have to come to the rescue.