--------------------------------------------------------------------
--               SRC Memory Interface Model
--
--
--------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

Entity memory_interface is
  port(Mclk     : in std_LOGIC;
       MDbus    : in std_logic;
       MDrd     : in std_logic;
       Strobe   : in std_logic;
       MDwr     : in std_logic;
       MDout    : in std_logic;
       MAin     : in std_logic;
       Reset    : in std_logic;
       Addr_Bus : out std_logic_vector(31 downto 0);
       Data_Bus : inout std_logic_vector(31 downto 0);
       SRC_Bus  : inout std_logic_vector(31 downto 0));
End memory_interface;


Architecture Rtl of memory_interface is

  signal ma_contents : std_logic_vector(31 downto 0);
  signal md_contents : std_logic_vector(31 downto 0);
  signal md_input    : std_logic_vector(31 downto 0);
  signal md_clock    : std_logic;

  begin

  Addr_Bus <= ma_contents;

  md_logic : process(MDbus, MDrd, strobe, Data_Bus, SRC_Bus)
  begin
    if(MDbus = '1') then
      md_input <= SRC_Bus;
    elsif(MDrd = '1') then
      md_input <= Data_Bus;
    else
      md_input <= "00000000000000000000000000000000";
    end if;

    if((MDbus = '1' or MDrd = '1') and Strobe = '1') then
      md_clock <= '1';
    else
      md_clock <= '0';
    end if;
  end process md_logic;

  md_register : process(Mclk,md_clock, Reset)
  begin
    if (Reset = '1') then
      md_contents <= "00000000000000000000000000000000";
    elsif (rising_edge(Mclk)) then
      if(md_clock = '1') then
        md_contents <= md_input;
      else
        md_contents <= md_contents;
      end if;
    end if;
  end process md_register;

  ma_register : process(Mclk,MAin, Reset)
  begin
    if (Reset = '1') then
      ma_contents <= "00000000000000000000000000000000";
    elsif (rising_edge(Mclk)) then
      if(MAin = '1') then
        ma_contents <= SRC_Bus;
      else
        ma_contents <= ma_contents;
      end if;
    end if;
  end process ma_register;

  md_tristate : process(md_contents,MDwr,MDout)
  begin
    if(MDwr = '1') then
      Data_Bus <= md_contents after Delay;
    else
      Data_Bus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    end if;

    if(MDout = '1') then
      SRC_Bus <= md_contents after Delay;
    else
      SRC_Bus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    end if;
  end process md_tristate;

end Rtl;