--------------------------------------------------------------------
--                    SRC Register File
--
-- 
--------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity register_file is
    port (Mclk     : in std_logic;
          Rsel0    : in std_logic;
          Rsel1    : in std_logic;
          Rsel2    : in std_logic;
          Rsel3    : in std_logic;
          Rsel4    : in std_logic;
          Rin      : in std_logic;
          Rout     : in std_logic;
          BAout    : in std_logic;
          Reset    : in std_logic;
          SRC_BUS  : inout std_logic_vector(31 downto 0):="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
end register_file;


architecture rtl of register_file is

  type register_array is array(31 downto 0) of std_logic_vector(31 downto 0);
  signal reg_contents : register_array;
  signal reg_sel_temp : std_logic_vector(4 downto 0);
  signal reg_sel : integer range 31 downto 0 ;

begin

  reg_sel_temp <= Rsel4&Rsel3&Rsel2&Rsel1&Rsel0;
  reg_sel <= To_Integer(unsigned(reg_sel_temp));

  register_load : process(Mclk, Rin, Reset)
  begin
    if(Reset = '1') then
      for I in 0 to 31 loop
        reg_contents(i) <= "00000000000000000000000000000000";
      end loop;
    elsif(rising_edge(Mclk)) then
      if(Rin = '1') then
        reg_contents(reg_sel) <= SRC_Bus;
      else
        reg_contents(reg_sel) <= reg_contents(reg_sel);
      end if;
    end if;
  end process register_load;

  reg_tristate : process(reg_contents,Rout,BAout,reg_sel)
  begin
     if(Rout = '1') then
       SRC_Bus <= reg_contents(reg_sel);
     elsif(BAout = '1' and reg_sel = 0) then
       SRC_Bus <= "00000000000000000000000000000000";
     elsif(BAout = '1' and reg_sel /= 0) then
       SRC_Bus <= reg_contents(reg_sel);
     else
       SRC_Bus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
     end if;
  end process reg_tristate;

end rtl;