--------------------------------------------------------------------
--               SRC Processor Model
--
-- 
--------------------------------------------------------------------


library IEEE ;
use IEEE.STD_LOGIC_1164.all;

entity src_cpu is
  port(clk       : in    std_logic;
       start     : in    std_logic;
       reset     : in    std_logic;
       memstrobe : in    std_logic;
       done      : in    std_logic;
       w         : out   std_logic;
       r         : out   std_logic;
       data      : inout std_logic_vector(31 downto 0);
       address   : out   std_logic_vector(31 downto 0)
      );
end src_cpu;

architecture rtl of src_cpu is

component control_unit
  port(mclk      : in   std_logic;
       start     : in   std_logic;
       reset     : in   std_logic;
       ir27      : in   std_logic;
       ir28      : in   std_logic;
       ir29      : in   std_logic;
       ir30      : in   std_logic;
       ir31      : in   std_logic;
       neq0      : in   std_logic;
       con       : in   std_logic;
       done      : in  std_logic;
       memstrobe : in  std_logic;
       w         : out std_logic;
       r         : out std_logic;
       pcin      : out std_logic;
       pcout     : out std_logic;
       irin      : out std_logic;
       c2out     : out std_logic;
       c1out     : out std_logic;
       gra       : out std_logic;
       grc       : out std_logic;
       grb       : out std_logic;
       baout     : out std_logic;
       rout      : out std_logic;
       rin       : out std_logic;
       mdrd      : out std_logic;
       mdout     : out std_logic;
       main      : out std_logic;
       mdbus     : out std_logic;
       strobe    : out std_logic;
       mdwr      : out std_logic;
       decr      : out std_logic;
       shld      : out std_logic;
       sc        : out std_logic;
       conin     : out std_logic;
       cout      : out std_logic;
       cin       : out std_logic;
       ain       : out std_logic;
       or_op     : out std_logic;
       and_op    : out std_logic;
       sub_op    : out std_logic;
       add_op    : out std_logic;
       ceqb_op   : out std_logic;
       not_op    : out std_logic;
       neg_op    : out std_logic;
       shr_op    : out std_logic;
       shc_op    : out std_logic;
       shl_op    : out std_logic;
       shra_op   : out std_logic;
       incr4_op  : out std_logic);
end component;

component alu
  port(Mclk     : in std_logic;
       Ain      : in std_logic;
       Cin      : in std_logic;
       Cout     : in std_logic;
       ADD_op   : in std_logic;
       CeqB_op  : in std_logic;
       Not_op   : in std_logic;
       Neg_op   : in std_logic;
       SHR_op   : in std_logic;
       SHC_op   : in std_logic;
       SHRA_op  : in std_logic;
       OR_op    : in std_logic;
       AND_op   : in std_logic;
       SHL_op   : in std_logic;
       SUB_op   : in std_logic;
       INCR4_op : in std_logic;
       Reset    : in std_logic;
       SRC_Bus  : inout std_logic_vector(31 downto 0));
end component;

component register_file
    port (Mclk     : in std_logic;
          Rsel0    : in std_logic;
          Rsel1    : in std_logic;
          Rsel2    : in std_logic;
          Rsel3    : in std_logic;
          Rsel4    : in std_logic;
          Rin      : in std_logic;
          Rout     : in std_logic;
          BAout    : in std_logic;
          Reset    : in std_logic;
          SRC_BUS  : inout std_logic_vector(31 downto 0));
end component;

component memory_interface
  port(Mclk     : in std_logic;
       MDbus    : in std_logic;
       MDrd     : in std_logic;
       Strobe   : in std_logic;
       MDwr     : in std_logic;
       MDout    : in std_logic;
       MAin     : in std_logic;
       Reset    : in std_logic;
       Addr_Bus : out std_logic_vector(31 downto 0);
       Data_Bus : inout std_logic_vector(31 downto 0);
       SRC_Bus  : inout std_logic_vector(31 downto 0));
end component;

component program_counter
  port(Mclk    : in std_logic;
       PCin    : in std_logic;
       PCout   : in std_logic;
       Reset   : in std_logic;
       SRC_Bus : inout std_logic_vector(31 downto 0));
end component;

component instruction_register
    port (Mclk     : in std_logic;
          IRin     : in std_logic;
          C1out    : in std_logic;
          C2out    : in std_logic;
          Gra      : in std_logic;
          Grb      : in std_logic;
          Grc      : in std_logic;
          Reset    : in std_logic;
          IR0      : out std_logic;
          IR1      : out std_logic;
          IR2      : out std_logic;
          IR27     : out std_logic;
          IR28     : out std_logic;
          IR29     : out std_logic;
          IR30     : out std_logic;
          IR31     : out std_logic;
          Rsel0    : out std_logic;
          Rsel1    : out std_logic;
          Rsel2    : out std_logic;
          Rsel3    : out std_logic;
          Rsel4    : out std_logic;
          SRC_BUS  : inout std_logic_vector(31 downto 0));
end component;

component cc_logic
  port(Mclk    : in std_logic;
       IR0     : in std_logic;
       IR1     : in std_logic;
       IR2     : in std_logic;
       Reset   : in std_logic;
       CONin   : in std_logic;
       CON     : inout std_logic;
       SRC_Bus : inout std_logic_vector(31 downto 0));
end component;

component shift_control
  port(Mclk    : in std_logic;
       Shld    : in std_logic;
       Decr    : in std_logic;
       Reset   : in std_logic;
       SC      : in std_logic;
       Neq0    : out std_logic;
       SRC_Bus : inout std_logic_vector(31 downto 0));
end component;

  signal src_bus : std_logic_vector(31 downto 0);
  signal gra_s, grb_s, grc_s, decr_s, shld_s, sc_s, main_s, mdout_s, conin_s, mdwr_s : std_logic;
  signal mdrd_s, strobe_s, mdbus_s, pcout_s, pcin_s, baout_s, rout_s, rin_s, irin_s : std_logic;
  signal c2out_s, c1out_s, cout_s, cin_s, ain_s, incr4_s, sub_s, shl_s, and_s, or_s : std_logic;
  signal shra_s, shc_s, shr_s, not_s, ceqb_s, add_s, neg_s, ir27_s, ir28_s, ir29_s : std_logic;
  signal ir30_s, ir31_s, neq0_s, con_s, ir2_s, ir1_s, ir0_s, rsel4_s, rsel3_s, rsel2_s : std_logic;
  signal rsel1_s, rsel0_s : std_logic;

begin

  cu1 : control_unit port map(mclk=>clk,start=>start,reset=>reset,ir27=>ir27_s,ir28=>ir28_s,
                              ir29=>ir29_s,ir30=>ir30_s,ir31=>ir31_s,neq0=>neq0_s,con=>con_s,
                              done=>done,memstrobe=>memstrobe,w=>w,r=>r,pcin=>pcin_s,pcout=>pcout_s,
                              irin=>irin_s,c2out=>c2out_s,c1out=>c1out_s,gra=>gra_s,grb=>grb_s,
                              grc=>grc_s,baout=>baout_s,rout=>rout_s,rin=>rin_s,mdrd=>mdrd_s,
                              mdout=>mdout_s,main=>main_s,mdbus=>mdbus_s,strobe=>strobe_s,
                              mdwr=>mdwr_s,decr=>decr_s,shld=>shld_s,sc=>sc_s,conin=>conin_s,
                              cout=>cout_s,cin=>cin_s,ain=>ain_s,or_op=>or_s,and_op=>and_s,
                              sub_op=>sub_s,add_op=>add_s,ceqb_op=>ceqb_s,not_op=>not_s,
                              neg_op=>neg_s,shr_op=>shr_s,shc_op=>shc_s,shl_op=>shl_s,
                              shra_op=>shra_s,incr4_op=>incr4_s);

  alu1: alu port map(mclk=>clk,ain=>ain_s,cin=>cin_s,cout=>cout_s,add_op=>add_s,ceqb_op=>ceqb_s,
                     not_op=>not_s,neg_op=>neg_s,shr_op=>shr_s,shc_op=>shc_s,shra_op=>shra_s,
                     or_op=>or_s,and_op=>and_s,shl_op=>shl_s,sub_op=>sub_s,incr4_op=>incr4_s,
                     reset=> reset,src_bus=>src_bus);

  rf1 : register_file port map(mclk=>clk,rsel0=>rsel0_s,rsel1=>rsel1_s,rsel2=>rsel2_s,
                               rsel3=>rsel3_s,rsel4=>rsel4_s,rin=>rin_s,rout=>rout_s,
                               baout=>baout_s,reset => reset, src_bus=>src_bus);
  
  mi1 : memory_interface port map(mclk=>clk,mdbus=>mdbus_s,mdrd=>mdrd_s,strobe=>strobe_s,mdwr=>mdwr_s,
                                         mdout=>mdout_s,main=>main_s,reset=>reset,addr_bus=>address,
                                         data_bus=>data,src_bus=>src_bus);

  pc1 : program_counter port map(mclk=>clk,pcin=>pcin_s,pcout=>pcout_s,reset=>reset,src_bus=>src_bus);

  ir1: instruction_register port map(mclk=>clk,irin=>irin_s,c1out=>c1out_s,c2out=>c2out_s,gra=>gra_s,
                                     grb=>grb_s,grc=>grc_s,reset=>reset,ir0=>ir0_s,ir1=>ir1_s,
                                     ir2=>ir2_s,ir27=>ir27_s,ir28=>ir28_s,ir29=>ir29_s,
                                     ir30=>ir30_s,ir31=>ir31_s,rsel0=>rsel0_s,rsel1=>rsel1_s,
                                     rsel2=>rsel2_s,rsel3=>rsel3_s,rsel4=>rsel4_s,src_bus=>src_bus);

  cc1 : cc_logic port map(mclk=>clk,ir0=>ir0_s,ir1=>ir1_s,ir2=>ir2_s,reset=>reset,
                          conin=>conin_s,con=>con_s,src_bus=>src_bus);

  sc1 : shift_control port map(mclk=>clk,shld=>shld_s,decr=>decr_s,reset=>reset,sc=>sc_s,
                               neq0=>neq0_s,src_bus=>src_bus);

end rtl;