PRELAB

1.  Read sections on Cache, System Integration Module, Timer Modules, DMA, and Debug Module of the MCF5307 User's Manual.
     Study the control signals used to interact with all these modules.
2.  Read Appendix D of SBC5307 User's Manual (Pin Array Layout).
3.  Reference the ColdFire Programmer's Reference Manual.
4.  Write the necessary programs required for each task in the lab.
5.  At the begining of the lab, the lab instructor will show you how to use the logic analyzer.  This instrument will be used to examine activities on the board.
 

INTRODUCTION

    The purpose of this lab is to give an overview of the ColdFire Processor and System Board.  The system has several modules, each of which controls a specific aspect of the overall functionality.  The modules examined in this lab are Unified Cache, System Integration Module, Timer Modules, DMA, and Debug Module.  Programs will be written to activate, deactivate, alter, read, and perform other operations on each module.  For some, the logic analyzer will be used to probe and examine various signals that are changed as the module is manipulated.  These signals can be probed via several connectors on the board.  The logic analyzer can be set up to display a timing diagram of the status of the probed signals.
 

USING THE LOGIC ANALYZER

    Power on the Logic Analyzer.  On the analyzer's connector's look for the Pod Number.  Numbers 1 and 2 correspond to the menu choice of Analyzer 1, while numbers 3 and 4 correspond to the menu choice of Analyzer 2.   Within the appropriate analyzer box, use the arrow keys to highlight the option "Type".  Press the "Select" button.  Using the arrow keys, select "Timing."  Again, using the arrow keys, move to the other analyzer window, highlight "Type", press "Select" button and select "Off".  Connect the analyzer connectors to the desired pins on the ColdFire board.  Don't forget to connect the GND connector.  The appropriate pins will be provided in the sections of the lab below, and can be referenced in Appendix D of SBC5307 User's Manual (Pin Array Layout).  Using the arrow keys, highlight "Run".  Press the "Select" button.  Choose "Repetitive" to see a running analysis of your signals.
 

DEBUG MODULE

    The debug module allows a user to view the processor status, such as its condition after halts and breakpoints in programs.  The debug module provides real time trace support and allows the user to see branch addresses and operand values.

    Procedure

    1.  The PST signals can be used to view the current state of the processor.  They are located on the connector J1 (see Appendix D of SBC5307 User's Manual).  Connect the logic analyzer's probes to these signals and watch their response.
    2.  Write a program that utilizes a breakpoint or Halt command.  Observe the resulting signal changes in PST[3:0] on the logic analyzer.  Demonstrate to the lab instructor.

    3.  Run your programs written for the pipeline lab again and measure the PST and DDATA signals to observe the signal changes.

    What happens to signals PST[3:0] when an halt or breakpoint is encountered?

What happens to signals PST and DDATA when a branch is taken?
 

TIMER MODULE

    The timer module includes two independant general-purpose 16-bit timers, as well as reference register, timer mode register, and event capture register.  The timer will count until a reference value set in the reference register is met.  Upon reaching this reference an interrupt can be generated.

    Procedure

    1.  Write a program that toggles the output bit TOUT on a pin in connector J8 when the timer reaches a given value.
    2.  Using TOUT, generate a square wave of 100 KHz.  Demonstrate this to your lab instructor.
    3.  Using TOUT, generate a square wave of 1.4 MHz.  Demonstrate this to your lab instructor.

    What value must be used by the timer register to generate a wave of 100 KHz?  A wave of 1.4 MHz?
 

DIRECT MEMORY ACCESS CONTROLLER (DMA)

    The DMA Controller provides a quick and efficient process for moving blocks of data with minimal processor overhead.  DMA can be used to perform a memory-to-peripheral transfer, or a memory-to-memory transfer.  A memory-to-memory transfer will be implemented in this lab.  The logic analyzer will not be needed.

    Procedure

    1.  Using the monitor command "bf", block fill a large section of memory with some data.  Write a program to perform a DMA transfer on this large block of data (at least 400 longwords) in memory to another section of memory.
    2.  Now, Program DMA by writing proper control word into its registers and fill your source block of memory with data using a DMA transfer.  Then perform a DMA transfer on this block and move it to another section of memory.

    Measure the timing of the two different transfer methods and observe the difference. You should use both Single-Address Transaction and Dual-Address Transactions DMA.
    How is DMA more efficient than this process?
 

SYSTEM INTEGRATION MODULE (SIM)

    The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire processor and peripherals.  This module contains a Module Base Address Register (MBAR) which is the base address of all internal peripherals and control registers.  The Software Watchdog Timer is a capability of the SIM that prevents system lockup should software become trapped in loops.  On detection of a loop exceeding a desired time limit, the Watchdog can either generate an interrupt to the processor or reset teh board.  This Watchdog Timer will be the focus of this portion of the lab.  The logic analyzer will not be needed.

    Procedure

    1.  Write a program that sets the Software Watchdog Timer to reset the board after a time corresponding to (2^9/system clock).  As a test loop, write to consecutive memory addresses until interrupted by the Watchdog.
    2.  Write a program that sets the Software Watchdog Timer to reset the board after a time corresponding to (2^28/system clock).  As a test loop, write to consecutive memory addresses until interrupted by the Watchdog.

    How many bytes of data does the loop get a chance to write before the board is reset in the first program?
    How many bytes of data does the loop get a chance to write before the board is reset in the second program?
 

CACHE MODULE

    The cache module maintains control of the ColdFire Processor's non-blocking, 8-KByte, 4-way set-associative cache.

    Procedure

     Write code to accomplish the following cache manipulations:

     1.  Disable, then Enable cache
     2.  Select writethrough, then copyback cache modes.

    What does unified cache mean?
     When a cache line is selected to host a new cache entry, what happens?
     What would the value of the CACR have to be to invalidate all of cache?
     Describe the two cache modes writethrough and copyback.