ELE537 VLSI System Design


Fall 1999 Syllabus

Wed. & Thur.  5-7PM,  Cherry Semiconductor, East Greenwich

Instructor: Dr. Jien-Chung Lo, Office: K211, Tel: (401) 874-2996, FAX: (401) 782-6422, email: jcl@ele.uri.edu

Office hours: TW 2-4PM

Answer to Mid-Term exam here (just the waveform for now).

This course will cover the system level design for VLSI. The use of hardware description language (IEEE's VHDL) and electronic design automation (EDA) tools in digital systems. The advanced analog system design and mixed-signal VLSI system design. The testing of VLSI systems and design for testability approaches.

Text Books:

  K. Skahill, VHDL for Programmable Logic, Addison-Wesley. (ISBN: 0-201-89586-2)
This book comes with Cypress's WARP2 software for PC Windows'95 or Sun Solaris. WARP2 can compile VHDL codes into target FPGA or CPLD and then perform function simulations.

J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, and Simulation, IEEE Press. (ISBN: 0-7803-3416-7; IEEE Product No.: PC5689-QAJ)

*Supplemental handouts will be distributed at class.

Useful Links

IEEE 1076.1 Analog and Mixed-Signal Extensions to VHDL

A tutorial for IEEE1076.1 (Need Java Script on)

The VHDL Synthesis Working Group (IEEE 1076.3)

EDA Industry Working Groups

Syllabus & Schedule Fall'99


week dates lectures text book
1 9/8, 9 Introduction to VLSI System Design N/A
2 9/15,16 Introduction to VHDL and WARP2 Skahill
3 9/22, 23 VHDL Models Skahill
4 - N/A
5 10/6, 7 VHDL Simulations Skahill
6 10/13, 14 VHDL Synthesis Skahill
7 10/20 Large Design Example Skahill
- 10/21 Mid-Term examination N/A
8 10/27, 28 CMOS devices Baker
9 - N/A
10 11/10 Analog CMOS  Baker
11 11/17,18 Switched Capacitor circuits Baker
12 11/24 Switched Current circuits Baker
13 12/1, 2 Mixed-Signal Circuits Baker
14 12/8 VLSI Testing N/A
- 12/9 Final examination N/A

Grading policy: Assignments 30%, Mid-Term 30%, Final 40%.

Disclaimer: The syllabus and schedule above are for reference only.

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