CMOS OpAmp driving a capacitive load of CL=5pF * Ao=10k, UGB=28MHz SR=+30V/us,-6V/us .include ~/magic/cmos50/models/t85r.md * Bias Circuitry mb1 b1 b1 Vdd Vdd pfet w=6 l=6 ad=30 pd=16 as=30 ps=16 mb2 b1 b1 b2 Vss nfet w=6 l=6 ad=30 pd=16 as=30 ps=16 mb3 b2 b2 Vss Vss nfet w=40 l=4 ad=200 pd=50 as=200 ps=50 * Differential Gain Stage m1 o1 Inn vs Vss nfet w=80 l=4 ad=400 pd=90 as=400 ps=90 m2 o2 Inp vs Vss nfet w=80 l=4 ad=400 pd=90 as=400 ps=90 m3 o1 o1 Vdd Vdd pfet w=100 l=4 ad=500 pd=110 as=500 ps=110 m4 o2 o1 Vdd Vdd pfet w=100 l=4 ad=500 pd=110 as=500 ps=110 m8 vs b2 Vss Vss nfet w=80 l=4 ad=400 pd=90 as=400 ps=90 * Output Stage m6a Out o2 Vdd Vdd pfet w=100 l=4 ad=600 pd=130 as=600 ps=130 m6b Out o2 Vdd Vdd pfet w=100 l=4 ad=600 pd=130 as=600 ps=130 m7 Out b2 Vss Vss nfet w=80 l=4 ad=400 pd=90 as=400 ps=90 * Phase Compensation m5 vc Vss o2 Vdd pfet w=8 l=4 ad=40 pd=18 as=40 ps=18 Cc Out vc 1.5p CL Out Gnd 5p VDD Vdd 0 dc 2.5 AC 0 VSS Vss 0 dc -2.5 AC 0 VDM Vdm 0 dc 0 AC 1 SIN(0u .6m 10k) VCM Vcm 0 dc 0 AC 0 RDM Vdm 0 1G VOS Inp Vos dc -25u Ep Vos Vcm Vdm 0 0.5 En Inn Vcm Vdm 0 -0.5 * Slew Rate Test in Unity-Gain Mode *VDM Vdm 0 DC 0 AC 1 PULSE(-.5 .5 1u 10n 10n 1u 2u) *Ep Vos Vcm Vdm 0 1 *En Inn Vcm Out 0 1 .OPTION SCALE=0.3U PROBE POST=1 .OP .MEAS AC PM1 find VP(Out) when VM(Out)=1 .MEAS PhaseMargin Param='180+PM1' .TRAN 1u 400u 200u .FOUR 10k V(Out) *.TRAN 20n 2.5u .DC VDM -1m 1m 5u .AC DEC 10 10 100meg .TF V(Out) VDM .NOISE V(Out) VDM 0 .PRINT TRAN V(Out) .PRINT DC V(Out) Power .PRINT AC VM(d1) VM(d9) VM(Out) VP(Out) .PRINT NOISE INOISE ONOISE .END