ELE545 Design of Digital Circuits

WF 2:00 - 3:40 PM, Kelley 103

Instructor: Dr. Jien-Chung Lo, Office: K-211, Tel: (401) 874-2996, FAX: (401) 782-6422

Office hours: WF 1-2 PM, Emails are welcome: jcl@ele.uri.edu


In this course students study advanced and recent topics on digital circuits. Starting from Quinn-McCluskey method, we will venture into area far beyond the basic logic designs. Students will learn about complex Boolean function manipulations, desgining strategies and automation algorithms. We will deal with both combinational and sequential circuit. We will study both designing and testing aspect of digital logic circuits. We shall review the IEEE VHDL standard that has been used as the hardware design laguage of the industry in recent years. Finally, we shall briefly examine some current and practical topics such as low power designs and asynchronous designs.

Text Book: E. J. McCluskey, Logic Design Principles: with emphasis on testable semicustom circuits, Prentice-Hall, 1986.


Syllabus & Schedule '97

week dates lectures text book
1 1/13 - 1/17 Numbers, codes, and switching algebra ch. 1&2
2 1/20 - 1/24 Analysis of combinational circuits ch. 3
3 1/27 - 1/31 Integrated circuits + special properites ch. 4&5
4 2/3 - 2/7 Combinational circuit design ch. 6.1 - 6.6
5 2/10 - 2/14 Combinational circuit design ch. 6.7 - 6.13
6* 2/17 - 2/21 Analysis of sequential circuits ch. 7
7 2/24 - 2/28 Sequential circuits ch. 8&9
8 3/3 - 3/7 review + Mid-term examination N/A
9 3/10 - 3/14 Spring recess N/A
10 3/17 - 3/21 Design for testability ch. 10
11 3/24 - 3/28 IEEE VHDL standard handouts
12 3/31 - 4/4 VHDL continue handouts
13 4/7 - 4/11 Low power logic designs handouts
14 4/14 - 4/18 Asynchronous logic designs handouts
15 4/21 - 4/25 Final project presentations handouts
- 5/9 Final Examination at 8 - 11 AM N/A

Grading policy: Homeworks 30%, Mid-Term 15%, Project 30%, Final 25%


Project Proposals are due 3/5; two days before Mid-term examination. Each team (or individual) should submit a title page contains project title and names of collaborators plus a 1-3 pages description of your porjeect goals and methodology.

Typical project topics: Survey of advanced design and test techniques in a specific area, using VHDL to verify a new design approach, analysis and comparative studies of current techniques, etc.


VHDL Cookbook and quick reference are now available here.


Links to Low Power related sites:


Links to Asynchronous Logic Designs related sites:


Disclaimer: The syllabus and schedule above are tentitive. They are for reference only.

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