More and more, improving uniprocessor performance depends on the exploitation of Instruction Level Parallelism (ILP), or that parallelism existing among the machine instructions of a program. However, little parallelism can be extracted if no attention is paid to the branches (control flow) of a program. In recent years, much progress has been made in reducing the ill effects of branches. The latest microprocessors, such as the Intel Pentium Pro, use sophisticated Branch Effect Reduction Techniques (BERTs) to achieve their high performance. Going way beyond such performance levels is the subject of our work; our latest research indicates that speedup factors in the 10's may be possible over sequentially operated machines; such speedups have been demonstrated in our initial simulations.
This course will survey the literature in the areas of instruction level parallelism and branch effect reduction. Each lecture will cover about 2 papers from the literature. Each session will consist of presentations of these papers by members of the class. Reading all the papers, joining the class discussion, and presenting some papers, constitute the work for the course.
Prerequisite: An undergraduate or graduate course in computer
architecture or the equivalent, or permission of instructor.
For example, if you have had the Hennessy and Patterson book:
``Computer Architecture, a Quantitative Approach'', in a course,
that's enough.
April 26, 1997 | Gus Uht | uht@ele.uri.edu