List of Publications

Journal Publications

  1. T. Xia and Jien-Chung Lo, "On-Chip Short Time Interval Jitter Measurement System for High-Speed Signal Timing Characterization," To appear in J. System Architecture, Elsevier Science.
  2. S. B. Ko and Jien-Chung Lo, "Efficient Realization of Parity Functions in FPGAs," J. Electronic Testing - Theory and Applications (JETTA), 20(5), pp. 489-499, Kluwer Academic Pub., October 2004.
  3. T. Xia and Jien-Chung Lo, "Time-to-Voltage Converter for On-Chip Jitter Measurement," IEEE Transactions on Instrument and Measurement, vol. 52, no. 6, pp. 1738-1748, December 2003.
  4. Jien-Chung Lo, "Analysis of a BICS-Only Concurrent Error Detection Method," IEEE Transactions on Computers, vol. 51, no. 3, pp. 241-253, March 2002.
  5. S.-B. Ko, Y.-Y. Guo and Jien-Chung Lo, "Studies of the SEMATECH IDDq Test Data," Journal of System Architecture, 47 (2002), pp. 831-846, Elsevier Science.
  6. Jien-Chung Lo, W. D. Armitage and C. S. Johnson, III, "Using Atomic Force Microscopy for Deep-Submicron Failure Analysis," IEEE Design and Test of Computers, pp. 10-18, Jan.-Feb. 2001.
  7. C. Metra and Jien-Chung Lo, "Intermediacy Prediction for High Speed Berger Code Checkers," J. Electronic Testing -- Theory and Applications (JETTA), pp. 607-615, 2000, Kluwer Academic Pub.
  8. A. G. Uht, Jien-Chung Lo, Y. Sun, J. C. Daly, and J. Kowalski, "Building Real Computer Systems," IEEE Micro, pp. 48-56, June 2000.
  9. Jien-Chung Lo, "On-Line Current Testing," IEEE Design and Test of Computers, pp. 49-56, October-December 1998.
  10. Jien-Chung Lo, "A Case Study of Self-Checking Circuits Reliability," VLSI Design, vol. 5, no. 4, pp. 373-383, 1998. (Gordan Breach Publishing)
  11. Jien-Chung Lo, "A Fast Binary Adder with Conditional Carry Generation," IEEE Trans. Computers, Vol. 46, No. 2, pp. 248-253, Feburary 1997.
  12. Jien-Chung Lo, "A Hyper Optimal Encoding Scheme for Self-Checking Circuits," IEEE Trans. Computers, Vol. 45, No. 9, pp. 1022-1030, September 1996.
  13. Jien-Chung Lo and E. Fujiwara, "Probability to Achieve TSC Goal," IEEE Trans. Computers, Vol. 45, No. 4, pp. 450-460, April 1996.
  14. Jien-Chung Lo, J. C. Daly and M. Nicolaidis, "A Strongly Code Disjoint Built-In Current Sensor for Strongly Fault-Secure Static CMOS Realizations," IEEE Trans. Computer-Aided Designs, Vol. 14, No. 11, pp. 1402-1407, November 1995.
  15. Jien-Chung Lo and J. H. Kim, "A Fault-Tolerant Associative Approach to Highly Available Memory Designs," Journal of Microelectronic Systems Integration, Plenum Publishers Inc, Vol. 3, No. 3, pp. 205-215, 1995.
  16. Jien-Chung Lo, D. W. Tufts and J. W. Cooley, "Active Nodal Task Seeking (ANTS): An approach to High-Performance, Ultra-Dependable Computing," IEEE Trans. on Aerospace Electronic Systems, Vol. 31, No. 3, pp. 987-997, July 1995.

Conference Presentations

  1. Jien-Chung Lo, Y.-L. Wan and E. Fujiwara, "Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes," IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 110-118, October 2005.
  2. T. Xia and Jien-Chung Lo, "On-chip short-time interval measurement for high-speed signal timing characterization," IEEE 12th Asian Test Symposium, pp. 326-331, November 2003.
  3. S. -B. Ko and Jien-Chung Lo, "A novel technology mapping method for AND/XOR expressions," IEEE Int'l Symp. Multiple-Valued Logic, pp. 133-138, May 2003.
  4. T. Xia and Jien-Chung Lo, "Long term jitter measurement for PLLs," IEEE North Atlantic Test Workshop, pp. 54-61, May 2003.
  5. T. Xia and Jien-Chung Lo, "On-chip jitter measurement for phase-locked loops," IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 399-407, November 2002.
  6. S.-B. Ko and Jien-Chung Lo, "Efficient Decomposition Techniques for FPGAs," IEEE 9th Int'l Conference on High Performance Computing, pp. 630-639, December 2002.
  7. S.-B. Ko and Jien-Chung Lo, "Decomposition Techniques based on Davio Expansion for FPGAs," IEEE North Atlantic Test Workshop, pp. 32-38, May 2002.
  8. S.-B. Ko, T. Xia and Jien-Chung Lo, "Efficient Parity Prediction in FPGA," IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 176-181, October 24-26, 2001.
  9. Y.-Y. Guo and Jien-Chung Lo, "Behavioral Fault Modeling of Analog Circuits," IEEE North Atlantic Test Workshop, pp. 52-57, May 2001.
  10. S. Li, K. Zhang and Jien-Chung Lo, “The 2nd Order Analysis of IDDQ Test Data,” IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 376-384, October 2000.
  11. S.-B. Ko and Jien-Chung Lo, “IDDQ Testing with Adaptive Threshold,”  IEEE North Atlantic Test Workshop, pp. 8-13, May 2000.
  12. W. D. Armitage and Jien-Chung Lo, “Erasure Error Correction with Hardware Detection,” IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 293-301, November 1999.
  13. Y.-Y. Guo and Jien-Chung Lo, “The Power Bus Stability Problem in Built-In Current Sensor Designs,”  IEEE North Atlantic Test Workshop, pp. 109-114, May 1999.
  14. Jien-Chung Lo, “Highly Reliable Systems with Differential Built-In Current Sensors,” IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 261-269, November 1998.
  15. Y.-Y. Guo and  Jien-Chung Lo, “Challenges of Built-In Current Sensor Designs,” IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 192-200, November 1998.
  16. C. Metra and Jien-Chung Lo, “Novel High-Speed Berger Code Checker,” Proc. IEEE 4th On-Line Testing Workshop, Italy, July 1998.
  17. Jien-Chung Lo, “Feasibility of a Redundancy Free Concurrent Error Detection Method,” Proc.  7th IEEE North Atlantic Test Workshop, May 1998.
  18. Y. -Y. Guo, Jien-Chung Lo, and C. Metra, “Fast and Area-Time Efficient Berger Code Checkers,” in Proc.  Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France, October 1997.
  19. P. Song and Jien-Chung Lo, “Realistic Faults Simulation for Standard Cell Library,” Proc. IEEE 6th North Atlantic Test Workshop, West Greenwich, RI, May 1997.
  20. Jien-Chung Lo, M. Kitakami and E. Fujiwara, “Reliable Logic Circuits using Byte Error Control Codes,” Proc.  Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 286-294, Boston, October 1996.
  21. P. Song and Jien-Chung Lo, “Test Sequence Generation for Realistic Faults in CMOS Based on Standard Cell Library,” Proc. Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 114-122, Boston, October 1996.
  22. P. Song and Jien-Chung Lo, “Standard Cell Based Test Generation for IDDQ Testing,” Proc. 2nd IDDQ Workshop, pp. 84-88. Washington, October 1996.
  23. C. Metra and Jien-Chung Lo, “Compact and High-Speed Berger Code Checker,” Proc. IEEE 2nd On-Line Testing Workshop, France, July 1996.
  24. P. Song, J. Hammen and Jien-Chung Lo, “Test Sequence Generation for Stuck-Open Faults in CMOS Circuits,” Proc. IEEE Atlantic Test Workshop, Hanover, NH, June 1996.
  25. Jien-Chung Lo, “Single Fault Masking Logic Designs with Error Correcting Codes,” Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 296-304, Lafayette, LA, October 1995.
  26. Jien-Chung Lo, “SFS Berger Encoded 2's Complement Modified Booth Array Multipliers with Wallace Tree,” Proc. IEEE 1st On-Line Testing Workshop, pp. 117-121, Nice, France, July 1995
  27. J. Hammen, P. Song and Jien-Chung Lo, “Test Generation Based on Test Profiles,” Proc. IEEE Atlantic Test Workshop, Hanover, NH, June 1995.