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ELE405 Digital Computer Design (3)
Hardware implementation of digital computers. Arithmetic circuits, memory
types and uses, control logic, basic computer organization, microprogramming,
input/output circuits, microcomputers.
(Lec. 3) Pre: ELE 305 and 306 and credit or concurrent enrollment in 406.
ELE 406 Digital Computer Design Lab (1)
Laboratory exercises related to topics in 405.
(Lab. 3)Pre: (305, 306 and (credit or concurrent enrollment in 405)) or permission of instructor.
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Course Description: After completing this course, you should
understand how a computer system is built and how it operates from the
viewpoints of the computer architect, the assembly language programmer, and
the logic designer. You will learn how to design the internal components of
a processor, including the datapath and control unit, the arithmetic logic
unit, and the memory system. You also will develop an understanding of the
performance and implementation trade-offs inherent in any computer design.
Laboratory:
The main software tool for this class is the Altera’s Quartus II.
Visit Altera's website for a free Quartus II web edition which runs on
any typical PC. Quartus II is a
comprehensive package includes schematic editor, state diagram editor, VHDL
entry and synthesis tool, integrated waveform and timing simulator, DSP
design tools and utilities, and FPGA implementation and configuration.
There will be four scheduled laboratories
to practice some advanced topics in VHDL and CPU designs.
Project:
Information about the project can be found here.
Students will first design and implement their CPUs from scratch. At the
second stage of the project, students are expected to build
prototypes of real-life computer-based systems using their own CPUs.
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The main hardware facility is the DE2 board from Altera. It carries a
Altera's Cyclone II EP2C35 FPGA in a 672-pin package. This FPGA has 33,216
programmable logic elements, 480K of on-chip RAM bits, 35 embedded 9-bit
multipliers, and four phase locked loops (PLLs).
The FPGA configuration file is downloaded from
the host computer via USB port.
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Time
& Location:
Lectures:
MWF 12:00-12:50 pm, Kelley 102.
Labs:
section 1: M 2:00 - 4:45 pm, Kelley 220.
section 2: Th 2:00 - 4:45 pm, Kelley 220.
Instructor:
Dr. Jien-Chung Lo
- Office: Kelley Annex 221
- Phone: x4-2996
- Email: jcl@ele.uri.edu
- Office Hours: MW 1-2pm
ELE406 Teaching Assistant:
Mr. Wenkai Wang
- Office: Kelley A3-4
- Email: Wenkai@ele.uri.edu
- Office hours: Thursday 12-2PM
Required
Texts:
1. "Computer Systems Design and Architecture," V. P. Heuring and
H. F. Jordan, 2nd Edition, Prentice Hall, 2004. ISBN: 0-13-048440-7.
2.
"The Designer's Guide to VHDL," Peter J. Ashenden, 2nd edition,
Morgan Kaufmann Publishers, 2002. ISBN: 1-55860-674-2.
3. " Pygmy CPU Manual,"
Supplemental Texts:
3.
"Computer Organization and Design: The Hardware/Software
Interface," D. Patterson and J. Hennessy, 2nd Edition,
Morgan Kaufmann Publishers, 1997. ISBN: 1-55860-428-6.
4.
"Rapid Prototyping of Digital Systems," J. O. Hamblen and M. D.
Furman, 2nd Edition, Kluwer Academic Pub., 2001. ISBN: 0-7923-7439-8. (available
in Computer Engineering Lab)
We will
be using the Heuring and Jordan
and the Ashenden books in this class. The Patterson and Hennessy book is optional
and is intended as another computer architecture reference.1.
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