ELE 447
Traffic Controller

Intersection of Rt. 1 & 138

James Fernstrom & Thomas Wenisch

Introduction

This design is a design for a traffic light control circuit for the intersection of Rt. 1 and Rt. 138 in South Kingston, RI. This circuit accepts input from sensors placed on the roadway at the intersection to detect the presence of waiting cars, and generates an output signal for each of the 18 lights at the intersection. In addition, the system allows the programmer to specify the maximum amount of time any car will have to wait for a green signal. Below is a diagram of the Rt 1 & 138 intersection. Lines with arrows indicate travel lanes and dark bars show the locations of the sensors. When a sensor is tripped, the lights will be triggered to give that direction a green light. When multiple sensors are pressed, a state machine (below) is used to determine the order in which the lights will signal. When no sensors are tripped, the North and South traffic on Rt. 1 is given a green light.






System Design

Below is a block diagram depicting the main components in the traffic light controller.



The large "PLA" block is a Programmable Logic Array which determines the next state for the state machine controlling the light and the output decoder which decodes the correct signals for each light based on the present state. The next state is based on the current present state and the conditions of the various sensors and the signal timer which advances the light from one state to the next.


This state diagram was used to generate a state table in EMACS which was then input into MPLA to generate a .MAG layout for the PLA.
The other main components in the design are the 5 present state flip-flops, 8 flip-flops which are set to 0 each 5 second clock interval and can be asynchronously reset to 1 whenever a car drives over one of the plate sensors. In addition a 5-bit counter is used to count the number of clock cycles since the lights transitioned from one phase to the next. After a certain number of cycles, the lights will be advanced to the next phase. This interval can be programmed using the 5 programming inputs into the Semi-Programmable Timer flip-flops. A comparator is used to compare the current timer count to the timeout value set by the programmer.

Pin Assignments


Pins 1-4,26-34,36-40 are output pins for each light signal.
Pin 9 is the system reset and allows testing of all lights.
Pins 10-14 are for programming the Signal Timeout value.
Pin 16 is the system clock (should be 0.2 Hz).
Pins 17-24 are the inputs from the plate sensors.
Pins 5,25 are Vdd.
Pins 15,35 are GND.

Layout

This diagram shows the Magic layout of the project.



Testing Procedure

Test Setup

  1. Connect Pins 5 and 25 to Vdd.
  2. Connect Pins 15 and 35 to GND.
  3. Connect a Green LED to the folowing pins:
  4. Connect a Red LED to the folowing pins:
  5. Connect a Yellow LED to the folowing pins:
  6. Connect a Normally-0 pushbutton to the following pins:
  7. Connect a DIP switch to the following pins:
  8. Connect the Y_Clk input (Pin 16) to a 0.2 Hz square wave clock signal.

Test Steps

  1. Push the Reset button to reset the system. All lights should be lit while Reset is depressed
  2. Set the Dip switches to "1100" (12 - 60 second timeout) and press the Strobe button
  3. Release the Reset button. North and South Green should be lit, all other directions should be red
  4. Press the East Plate button. North and South should become yellow. After 5 seconds, they should become Red and the East signal should become Green. 15 seconds later, the West signal should become green. Then, after the Signal timeout period has expired (60 seconds), the East and West signals should become Yellow, and then Red, and North and South should become Green.
  5. Now press the North Left Plate button. South should become Yellow, then Red. North Left should become Green. North should remain Green. After the Signal timeout has expired, North Left should become Yellow, then Red and South should become Green.


Conclusions

This design functioned properly in structural (hSpice) siumulation. In addition to testing the full design, we also separately tested the PLA when it was first created to verify that it functioned properly.
We began the design with a very high level look at the intersection and how we felt cars should be allowed to proceed. From this analysis, we developed a state diagram in a diagramming tool which detailed the flow from one signal phase to the next. This diagram was then turned into a state table from which we made the input file for the PLA.
We had numerous problems with components in the URI Cell library, mostly due to components being extracted with older versions of Magic. In order to alleviate these problems, we flattened our design to a single component by dumping all subcells before extracting.
A possible future enhancement for our design would be to include a watchdog circuit which would detect fault conditions (failed lights or error conditions such as a red and green light being lit in the same direction). This circuit could then display an error message via an alarm signal to the signal programmer and flash the red lights in every direction as a warning to the public.