Welcome to the High Performance Computing Laboratory!
logo by Laurette Bradley & Gus Uht
University of Rhode Island|
Department of Electrical and Computer Engineering
Tel: (401)874-5880/2505, Fax: (401) 782-6422
4 East Alumni Ave., Kingston, RI 02881-0805
- Qing (Ken) Yang:
Director, Distinguished Engineering Professor, firstname.lastname@example.org;
- Jien-Chung Lo:
- Augustus K. Uht: Research Professor, email@example.com;
Yan Lindsay Sun
: Assistant Professor, firstname.lastname@example.org;
- Yiming Hu, Ming Zhang, Xubin He, Weijun Xiao, Jin Ren, Tim Parys, Yinan Liu, Michael Smith
Download Block Level Unlimited Versioning System Demo Here
Download REAPIT (Replay EHR at Any-Point-In-Time) here.
Download the TRAP demo program. The program is a working iSCSI target for Windows with Continuous Data Protection functionality
- What does "TRAP" stand for? It is an abbreviation of
"Timely Recovery to Any Point-in-time"
The Following are a few papers explaining TRAP in detail:
"TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in
in The 33rd Annual International Symposium on Computer Architecture, 2006 (ISCA'
Qing Yang, Weijun Xiao, and Jin Ren
"PRINS: Optimizing Performance of Reliable Internet Storages"
The 26th International Conference on Distributed Computing Systems, Lisbon, Port
ugal, 2006. (ICDCS'06).
Qing Yang, Weijun Xiao, and Jin Ren
"Implementation and Performance Evaluation of Two Snapshot Methods on iSCSI Target Storages,"
In NASA/IEEE MSST2006,
Weijun Xiao, Yinan Liu, Qing (Ken) Yang, Jin Ren and Changsheng Xie
Source code for the snapshot implementation.
- "I-CASH: Intelligently Coupled Array of SSD and HDD"
in The 17th IEEE International Symposium on High Performance Computer
Architecture, 2011 (HPCA'11).
Jin Ren and Qing Yang
Download the I-CASH Program here.
Optimized Computation on GPUs:
By better utilizing memory hierarchy and communication structure,
optimal computations of typical signal processing algorithms have been carried out on GPUs.
The CAT cache
is a new cache orgainization invented by the research group led by Prof. Yang.
The main advantage of this cache structure is that it saves chip area for
implementing cache tags by an order of magnitude.
The Prime-mapped Cache
is a new cache organization for vector processing.
It minimizes cache misses caused by line conflicts.
U.S. Patent and Trademark Office, No. 5,379,393
The DCD Project
DCD is a new hard disk drive structure that improves write performance of current
state-of-the-art disks by 200 times, YES, 200 times not 200%!
The US patent for this new technology was approved by the
U.S. Patent and Trademark Office, No. 5,754,888 in September 1997.
RAPID Cache is a new disk cache structure for RAID systems. It reduces system cost,
increases throughput and reliability of RAID systems.
U.S. Patent and Trademark Office,
No. 6,243,795, June 5th, 2001.
``STICS-----SCSI-To-IP Cache Storage"
ETAN Grant Challenge!
We run the ETAN Rating Grant Challenge from April 25, 2007 to July 15, 2007. The
ETAN Rating Challenge seeks smart and powerful attacks against on-line rating systems. If you can mislead the rating system more than other participating teams, you win the cash prizes and winner certificate. The attacking data provided by you will be used to evaluate existing algorithms, and help us to design more reliable on-line rating systems. Why participate? Cash, Fame, Good Cause, and Having Fun!
Apache Web Server Study
As part of joint research program with IBM, we have studied the most popular
web server: Apache. Several performance enhancements have been proposed.
Parallel/Distributed Processing (ANTS)
Fault Tolerant Computing
Order of magnitude ILP (Instruction Level Parallelism): the
for how this is done.
National Science Foundation, Office of Naval Research, Intel Corp and IBM Corp.
RELATED GRADUATE AND UPPER-DIVISION COURSES
- ELE 405 Digital Computer Design
- ELE 408 Computer Organization Laboratory
- ELE 437 Computer Communications
- ELE 447 VLSI Design and Simulation
- ELE 537 VLSI System Design
- ELE 542 Fault-Tolerant Computing
- ELE 543 Computer Networks
- ELE 544 Computer Arithmetic for VLSI
- ELE 545 Design of Digital Circuits
- ELE 546 Computer-Based Instrumentation
- ELE 548 Computer Architecture
- ELE 549 Computer System Modeling
- ELE 581 Special Topics in Artificial Intelligence
- ELE 648 Advanced Topics in Computer Architecture
- ELE 658 Instruction Level Parallelism
hits since August 5, 1996.
May, 2006 |
Qing Yang |