Areas:

  1. Instruction Level Parallelism (ILP) and Supercomputing
  2. Adaptive Computing and Underclocking
  3. Memory System Performance
  4. Network Security and Wireless Communications
  5. Multithreaded Architecture
  6. Simulation

Instruction Level Parallelism (ILP) and Supercomputing:
Projects Talks

A. K. Uht, "Multipath Execution," in Speculative Execution in High Performance Computer Architectures, D. Kaeli and P.-C. Yew, Eds. Boca Raton, FL, USA: CRC Press, August 2004. Invited chapter; in press.

J. J. Yi, R. Sendag, D. J. Lilja, "Instruction Precomputation: Dynamically Removing Redundant Computations Using Profiling," in Speculative Execution in High Performance Computer Architectures, D. Kaeli and P.-C. Yew, Eds. Boca Raton, FL, USA: CRC Press, August 2004. Invited chapter; in press.

A. K. Uht, "Teradactyl: an Easy-to-Use Supercomputer," in Proceedings of the International Symposium of Santa Caterina on Challenges in the Internet and Interdisciplinary Research (SSCCII-2004). Amalfi, Italy: IPSI, January-February 2004. Invited and refereed paper.

A. K. Uht, D. Morano, A. Khalafi, and D. R. Kaeli, "Levo - A Scalable Processor With High IPC," The Journal of Instruction-Level Parallelism, vol. 5, August 2003. (http://www.jilp.org/vol5).

D. Morano, A. Khalafi, D. R. Kaeli, and A. K. Uht, "Realizing High IPC Through a Scalable Memory-Latency Tolerant Multipath Microarchitecture," in Proceedings of the Workshop On Chip Multiprocessors: Processor Architecture and Memory Hierarchy Related Issues (MEDEA2002), at PACT 2002. Charlottesville, Virginia, USA, September 22, 2002. Also appears in ACM SIGARCH Computer Architecture Newsletter, March 2003.

A. Uht, A. Khalafi, D. Morano, M. d. Alba, and D. Kaeli, "Realizing High IPC Using Time-Tagged Resource Flow Computing," in Proceedings of the Euro-Par 2002 Conference, Springer-Verlag Lecture Notes in Computer Science. Paderborn, Germany: ACM, IFIP, August 28, 2002, pp. 490-499.

J. J. Yi, R. Sendag, and D. J. Lilja, "Increasing Instruction-Level Parallelism with Instruction Precomputation," in Proceedings of the Euro-Par 2002 Conference, Springer-Verlag Lecture Notes in Computer Science. Paderborn, Germany: ACM, IFIP, August 28, 2002, pp. 481-485.

A. K. Uht, S. Langford, and D. Morano, "Interactive High-Performance Processor Understanding via the Web," in Proceedings of the SSGRR 2002w International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet. L'Aquila, Italy: Telecom Italia, January 21-27, 2002. LevoVis paper.

A. K. Uht, A. Khalafi, D. Morano, T. Wenisch, M. de Alba, and D. Kaeli, "Levo: IPC in the 10's via Resource Flow Computing," IEEE TCCA Newsletter, Special Issue, December 2001. Presented at PACT 2001 Work-In-Progress (WIP) Session, September 2001.

A. K. Uht, V. Sindagi, and S. Somanathan, "Branch Effect Reduction Techniques," IEEE COMPUTER, vol. 30, no. 5, pp. 71-81, May 1997.

A. K. Uht and V. Sindagi, "Disjoint Eager Execution: An Optimal Form of Speculative Execution," in Proceedings of the 28th International Symposium on Microarchitecture (MICRO-28). Ann Arbor, MI, November/December 1995, pp. 313-325.



Adaptive Computing and Underclocking:
Projects Talks

A. K. Uht, "Uniprocessor Performance Enhancement Through Adaptive Clock Frequency Control," IEEE Transactions on Computers, 2005. In Press.

A. K. Uht and R. J. Vaccaro, "TEAPC: Adaptive Computing and Underclocking in a Real PC," in Proceedings of the First IBM P=ac2 Conference. Yorktown Heights, NY, USA: IBM T.J. Watson Research Center, October 6-8, 2004, pp. 45-54.

A. K. Uht, "Going Beyond Worst-Case Specs with TEAtime," Computer, vol. 37, no. 3, pp. 51-56, March 2004. Invited paper for Special Issue on ``Better Than Worst-Case Design''.

A. K. Uht, "Uniprocessor Performance Enhancement Through Adaptive Clock Frequency Control," in Proceedings of the SSGRR-2003w International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet. L'Aquila, Italy: Telecom Italia, January 6-12, 2003. Invited and refereed paper.



Memory System Performance:

P. Chuang, R. Sendag, and D. J. Lilja, "Improving Data Cache Performance via Address Correlation: An Upperbound Study," in Proceedings of the Euro-Par 2004 Conference, Springer-Verlag Lecture Notes in Computer Science. Pisa, Italy: ACM, IFIP, September 2004.

R. Sendag, P. Chuang, and D. J. Lilja, "Address Correlation: Exceeding the Limits of Locality," in IEEE Computer Architecture Letters, May 2003.

K. Wu, R. Sendag, and D. J. Lilja, "Exploring the Memory Access Regularity in Pointer-Intensive Application programs," in Proceedings of the IDEAL 2003 Conference, March 2003.

R. Sendag, D. J. Lilja, and S. R. Kunkel"Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions," in Proceedings of the Euro-Par 2002 Conference, Springer-Verlag Lecture Notes in Computer Science. Paderborn, Germany: ACM, IFIP, August 28, 2002, pp. 468-480.



Network Security and Wireless Communications:
Projects

W. Yu, Yan Sun, and K.J. Ray Liu, "HADOF: Defense Against Routing Disruptions in Mobile Ad Hoc Networks", to appear, IEEE INFOCOM (acceptance ratio 17%),  March, 2005.

Yan Sun, Wade Trappe, and K.J. Ray Liu, "A Scalable Multicast Key Management Scheme for Heterogeneous Wireless Networks", Vol. 12, No.4, pp 653-666 IEEE/ACM Transactions on Networking, August 2004.

Yan Sun, and K. J. Ray Liu, "Securing Dynamic Membership Information in Multicast Communications", in Proc. IEEE INFOCOM (acceptance ratio 18%), Hong Kong, March 2004.

Yan Sun, and K. J. Ray Liu, "Scalable Hierarchical Access Control in Secure Group Communications", in Proc. IEEE INFOCOM (acceptance ratio 18%), Hong Kong, March 2004.

Y. Mao, Yan Sun, Min Wu and K. J. Ray Liu, "Dynamic Join and Exit Amortization and Scheduling for Time-Efficient Group Key Agreement", in Proc. IEEE INFOCOM (acceptance ratio 18%), Hong Kong, March 2004.

C. Pandana, Yan Sun and K. J. Ray Liu, "Channel-Aware Priority Transmission scheme using Joint Channel Estimation and Data Loading over OFDM systems", accepted, IEEE Transactions on Signal Processing, 2004.



Multithreaded Architectures:

R. Sendag, Y. Chen, and D. J. Lilja, "The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture," in IEEE Transactions on Parallel and Distributed Systems, 2005. In press.

Y. Chen, R. Sendag, and D. J. Lilja, " Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor," in Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS 2003), April 2003.

R. Sendag, Y. Chen, and D. J. Lilja, "The Effect of Executing Mispredicted Load Instructions on Speculative Multithreaded Architecture," in Proceedings of the 6th Workshop on Multi-threaded Execution, Architecture and Compilation, held in conjunction with IEEE MICRO-35, November 2002.



Simulation:

J. J. Yi, S. Kodakara, R. Sendag, D. J. Lilja, and D. M. Hawkins, "Characterizing and Comparing Prevailing Simulation Techniques," in Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA-11), February 2005.