Title:   Analyzing Critical Circuit Path Test Coverage
Authors: Carol Stolicny, Compaq Computer Corp.
         *William Grundmann, Compaq Computer Corp.
Contact: carol.stolicny@compaq.com, william.grundmann@compaq.com

Abstract:
This paper describes a unique but simple method for ensuring test pattern
coverage of critical circuit delay paths in a design. By extending the
design timing-verification processes, we develop a new logic network for
the design that abstracts and identifies the activation of a critical path.
This network, a path delay fault model, is then applied within the
traditional stuck-at fault simulation framework to perform critical path
coverage analysis. Although the method's basic operation is derived from
delay timing verification, it is implemented in a cycle-friendly simulator
and does not require the simulation of any gate or interconnect delays or
latch setup and hold times.