Title:   Array Modeling for Test and Verification
Authors: *Tom Ziaja, IBM-Austin TX
Contact: tziaja@us.ibm.com

Abstract:
Arrays are used extensively in microprocessors, from smaller register files
to large on-chip data and instruction caches. For high performance, and to
achieve very dense designs, these circuits are typically custom designs.
Because of these characteristics it is often a difficult process to verify
that the logic design of an array matches its circuit function. The complex
circuit design makes low-level simulation essential. We have developed a
process that approaches this problem in two stages. First, the design of the
array circuit is required to coincide with a corresponding logic design at
an abstract logical read/write array boundary. Then, ATPG test patterns are
generated and simulated against a VerilogŪ structural model derived from the
circuit design. With this process, we have an objective measure and high
confidence that the logic matches the circuit behavior during LSSD scan test,
and can also simulate functional patterns for stuck-fault coverage to grade
the array testability. We are currently using this methodology with great
success for the arrays in our custom processor designs.