Title:   Methodology For Design Verificaiton For A Lab. Debug Environment
Speaker: Andreas S Meyer, ASIC Alliance Corp., MA

Abstract:
Recent trends in high-level design have outpaced advances in
the ability to effectively verify system design intent.  Future
projections show this problem will become the single gating
item in SoC design.  Among the biggest problems in this area
is debugging first silicon in the lab.  This talk will discuss
the interaction between requirements for high level design
verification, and those for debug and diagnosis in the lab.