Title:   Incorporating Place-and-Route and Power Constraints in 
         System-on-a-Chip Test Access Architectures
Authors: *Krishnendu Chakrabarty, Duke Univ.
Contact: krish@ee.duke.edu

Abstract:
Test access is a difficult problem encountered in the testing of
core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC
are not directly accessible via chip inputs and outputs, special access
mechanisms are required to test them at the system level. We propose test
access architectures based on integer linear programming (ILP) that
incorporate place-and-route constraints arising from the functional
interconnections between cores, as well as system-level constraints on
power consumption.  As a case study, we apply the ILP models to two
representative SOCs, and solve them using a public-domain ILP software
package.