Title:   Correlation-Based Test Generation for Sequential Circuits
Authors: Ashish Giani, Shuo Sheng and *Michael Hsiao, Rutgers Univ.
         Vishwani Agrawal, Lucent Bell Labs.
Contact: ashishg@ece.rutgers.edu, va@research.bell-labs.com,
         shuo@ece.rutgers.edu,  mhsiao@ece.rutgers.edu

Abstract:
We present a new test generation procedure for sequential circuits using
vector correlation. Two types of correlations, namely, spatial correlation
between the bits of the same vector and temporal correlation between the
same bit position of different vectors, are considered.  From an initial
vector set, unnecessary vectors are removed by using a fault simulator
based compactor that preserves the fault coverage.  The compacted set is
then used to empirically determine spatial and temporal correlations. 
These correlations modify an otherwise random vector source to generate
new vectors, which are subsequently compacted.  Repeated application of
correlation analysis, vector generation and compaction produces
significantly high fault coverage using relatively small computing
resources. These results show improvements of fewer vectors for the same
high coverage, in comparison to many previously reported test generation
programs based on genetic algorithms or compaction techniques.  We
obtained  these improvements consistently for several other benchmark
circuits.