Title:   Accelerating Test Generation by VLSI Hardware Emulation
Authors: *Morteza Fayyazi and Zainalabedin Navabi, NorthEastern Univ.
Contact: mfayyazi@ece.neu.edu, navabi@ece.neu.edu

Abstract:
A hardware emulation system based on a programmable VLSI array is
used for test pattern generation for combinational circuits. The
real-time simulation capability of the hardware emulator significantly
improves time required for test generation. The VLSI hardware emulator
implements a parallel algorithm for test pattern generation based on
neural networks. Test generation is achieved by mapping a circuit into
its equivalent VLSI array test generation model emulating this test
generation algorithm. The programmed array serves as a hardware
accelerator for automatic test pattern generation.