Title:   A Generalized Hold Method for Random Pattern Testing of 
         Sequential Circuits and its BIST Implications
Authors: *Shambhu J. Upadhyaya, SUNY-Buffalo
Contact: shambhu@cse.buffalo.edu

Abstract:
A technique called the hold method in which signals at primary inputs
and scan flip-flops of a partially scanned sequential circuit are held
for a certain length of time has been proposed earlier. This paper 
presents a systematic scheduling of the hold method test application 
which results in fault coverage improvements with no additional cost. 
The benefits are demonstrated by experiments on ISCAS89 benchmark 
circuits as well as on some commercial circuits. The suitability of 
the technique for the built-in self-test implementation is also 
studied.