Title:   BIST Coverage Improvement for the IBM S/390 G6 637 MHz 
         Microprocessor
Authors: *Richard F. Rizzolo, IBM-Poughkeepsie NY
         Bryan J. Robbins, IBM-Poughkeepsie NY
         Richard M. Gabrielson, IBM-Endicott NY
         Joseph Swenton, IBM-Endicott NY
Contact: brobbins@us.ibm.com

Abstract:
In this paper we describe methods that were used to decrease the number of
logic BIST untested faults by 60% without any schedule impact. 	One of these
methods, improving random pattern testability using an IBM TestBench 
product -RRFA- is the focus.  It was used successfully on four chips with
greater than 10 million logic transistors.  We believe that increasing BIST
coverage is a strategic direction that will decrease system test fallout,
improve system test diagnostics, and reduce reliance on VLSI testers
with special WRP hardware.