The 9th IEEE North Atlantic Test Workshop

May 25 - May 26, 2000

Ocean View Inn & Resort, Gloucester, Massachusetts

Sponsored by the IEEE Computer Society , Test Technology Technical Council
and Tufts University.

The IEEE North Atlantic Test Workshop provides a forum for discussions on the latest issues relating to higher quality, more economical, and more efficient testing methodologies and designs. The 9th workshop will focus on `Testing Challenges for the New Millennium'.

FINAL PROGRAM Thursday, 05/25/2000

08:30 - 09:30   Welcome
                Invited Talk: Rick Chrusciel, Senior Logic Product Specialist, Advantest-America Inc.
                Topic: Development of a 1GHz High Speed Logic Test System

09:30 - 09:40 Break

09:40 - 11:40   Session 1: Defect Modeling and IDDQ/Path/Delay Test
                      Chair: Ray Bulaga, IBM
                      Co-Chair: Krishnendu Chakrabarty, Duke Univ.

1.1    Mutation Analysis for Functional Defect Modeling,
         *Ian Harris and Qinshmang Zhang, UMass
1.2    IDDQ Testing with Adaptive Threshold,
         *Seok-Bum Ko and J. C. Lo, Univ. Rhode Island
1.3    A New Scan Structure for Improved Scan Chain Diagnosis and Delay Fault Coverage,
        *Peilin Song, IBM-Poughkeepsie NY
1.4    Analyzing Critical Circuit Path Test Coverage,
         Carol Stolicny and *William Grundmann, Compaq Computer Corp.

11:45 - 13:00 Lunch

13:00 - 16:00 Moby Duck Tour & Free Time

16:00 - 17:30   Session 2: Memory Modeling and Test
                      Chair: Shambhu J. Upadhyaya, SUNY-Buffalo
                      Co-Chair: Leo Brooks, AMCC

2.1    Array Modeling for Test and Verification, *Tom Ziaja, IBM-Austin TX
2.2    Detecting Inter-Port Faults in Multi-Port Memories, J. Zhao, Texas A&M Univ.
         S. Irrinki and M. Puri, LSI Logic and *Fabrizio Lombardi, NorthEastern Univ.
2.3    Self Test Architecture for Testing Complex Memory Structures, *Kamran Zarrineth,
         Thomas Eckenrode, Steven Gregor, IBM-Endicott, and R. Dean Adams, IBM-Burlington

17:30 - 18:30 Session 3: Special Presentations
Chair: Vishwani Agrawal, Bell Labs, Lucent Technologies

3.1 Memory Test with SOI Technology
Speaker: R. Dean Adams, IBM - Burlington, VT

18:30 - 20:00 Dinner

20:00 - 22:00 Session 3: Special Presentations (Continue)

3.2    Built-In Self-Test: Past, Present and Future,
         Speaker: Dr. Jacob Savir, NJIT
3.3    Methodology For Design Verificaiton For A Lab. Debug Environment,
         Speaker: Andreas S Meyer, ASIC Alliance Corp., MA

Friday, 05/26/2000

08:30 - 09:30 Keynote Address: George Chamillard, President & CEO, Teradyne
Topic: Meeting the Challenges of Testing Today's and Tomorrow's Chips and Circuit Boards

09:30 - 09:40 Break

09:40 - 11:40   Session 4: System/Core Test, BIST and Tester Software
                      Chair: Shianling Wu, Lucent Bell Labs.
                      Co-Chair: Peilin Song, IBM

4.1    Incorporating Place-and-Route and Power Constraints in System-on-a-Chip Test Access Architectures,
         *Krishnendu Chakrabarty, Duke Univ.
4.2    Serial Data Compression for 1149.1 Compatible Core Testing,
        *Zainalavedin Navabi and Farzin Karimi, Northeastern Univ.
4.3    Effective Parallel Processing Techniques for The Generation of Test Data for Logic Built-in Self Test System,
         *Paul Chang, Intel Corp., Austin, TX
4.4    Viewpoint -- A Software System for a High Performance Tester Family,
         *Yuhai Ma, Advantest of USA

11:40 - 13:00 Lunch

13:00 - 14:30   Session 5: Test Generation and Development
                      Chair: Paul Chang, Intel
                      Co-Chair: Michael Hsiao, Rutgers Univ.

5.1    Correlation-Based Test Generation for Sequential Circuits,
         Ashish Giani, Shuo Sheng and *Michael Hsiao, Rutgers Univ. Vishwani Agrawal, Lucent Bell Labs.
5.2    Accelerating Test Generation by VLSI Hardware Emulation,
         *Morteza Fayyazi and Zainalabedin Navabi, NorthEastern Univ.
5.3    Test Development for High Performance VLSI Digital Signal Processors,
         *M. Michael Vai, Huy T. Nguyen, and William S. Song, MIT Lincoln

14:30 - 14:40 Break

14:40 - 16:10   Session 6: Random Pattern Test
                      Chair: Richard Davies, Compaq
                      Co-Chair: Ian Harris, UMass-Amherst

6.1    A Generalized Hold Method for Random Pattern Testing of Sequential Circuits and its BIST Implications,
         *Shambhu J. Upadhyaya, SUNY-Buffalo
6.2    BIST Coverage Improvement for the IBM S/390 G6 637 MHz Microprocessor,
         *Richard F. Rizzolo, and Bryan J. Robbins, IBM-Poughkeepsie NY, and
         Richard M. Gabrielson, and Joseph Swenton, IBM-Endicott NY
6.3    Techniques for the Generation of Highly Efficient Weighted Random Pattern Tests,
         *Paul Chang, Intel Corp., Austin, TX