4.1 - Test Access Architectures for System-on-a-Chip Designs

Authors: Krishnendu Chakrabarty
Univ/Comp: Duke Univ.
Presenter: Krishnendu Chakrabarty - krish@ee.duke.edu

******** Abstract:
System-on-a-chip designs containing embedded cores pose difficult test
challenges. In order to reduce test costs and meet demands for short
time-to-market, the testing time for a core-based system should be
minimized by adopting an appropriate test access architecture. We address
several problems related to the design of optimal test architectures. We
develop integer linear programming (ILP) models for these problems and
solve them using a representative ILP software package for a non-trivial,
core-based system.