4.2 - Standard for Testing Cores, Are We on the Right Boat?

Authors: Sudipta Bhawmik and Shianling Wu
Univ/Comp: Bell Labs, Lucent Technologies
Presenter: Shianling Wu - shianlingwu@lucent.com

******** Abstract:
Designing ASIC has never been so challenging especially with
reusing Intellectual Property (IP) cores becoming a reality.
Core Based Design (CBD) is chanted as the technique to truly take
advantage of the IP cores to produce desired System on Chip (SoC).
One key challenges of CBD/SoC is how to test those portions of the logic
that is NIH (not invented here). Many industry wide activities are
forging ahead under this umbrella: to name a few, Virtual Socket
Interface Alliance (VSIA), IEEE P1500 - Standards for Embedded Core Test,
and Reusable Application-Specific Property Developer (RAPID).
This presentation discusses an overview of those programs, their
particular focus on test, and pros, cons and potential holes.