4.3 - Testing Complex System on a Chip ASIC Products Incorporating Video DACs

Authors: Bruce Cowan, James Monzel, Mark Styduhar, Ray Bulaga, Leo Brooks
Univ/Comp: IBM
Presenter: Bruce Cowan - bcowan@btv.ibm.com

******** Abstract:
This paper describes a design for test solution for complex mixed signal
ASIC chips containing embedded Video Digital-to-Analog Converter (VDAC)
cores. The VDAC core's Built-In Test (BIT) logic makes it possible to use
common digital tester hardware and interfaces for complete testing of the
DAC. ATPG tools and Level Sensitive Scan Design (LSSD) test techniques are
used to generate test patterns for the User Defined Logic (UDL) and the
core's digital logic. The BIT initialization sequence and clock protocols
required to run the BIT are defined at the core's boundary and then
expanded by a unique automated mapping tool and converted to test sequences
that can be applied to the ASIC package pins, making use of the scannable
latches in the core and surrounding logic. Since the process is automated
test pattern generation of the entire ASIC (UDL + Core) is accomplished
with no manual intervention.