5.4 - Design and Implementation of a Parallel Weighted Random Pattern and
       Logic Built In Self Test

Authors: Paul Chang, Brion Keller and Sarala Paliwal
Univ/Comp: IBM
Presenter: Sarala Paliwal - paliwals@us.ibm.com

******** Abstract:
An increase in chip densities has led to a significant increase in test
generation and fault simulation times. Analysis of various test
methodologies has shown that Logic Built in Self Test(LBIST) and Weighted
Random Pattern Test(WRPT) are a significant portion of the execution time.
Several parallel algorithms have been proposed to reduce run times for ATPG.
This paper for the first time describes the parallelization of the LBIST
and WRPT algorithms. Results on industrial circuits that range in size
from 300,000 gates to about 1 million gates are presented. Previous works
have published results on parallelization of deterministic testing and
simulation for smaller circuits.