Welcome to IEEE TCCA Email-Monthly, Sept. 2002:
submitted by: Alex Orailoglu <wasp1@dna.ucsd.edu>
Call for paper: http://dna.ucsd.edu/wasp1
2. IEEE Computer Magazine: Special Issue on
"Hardware/Software Co-Design: Techniques,
Tools and Architectures"
submitted by: Mainak Sen <mainak@eng.umd.edu>
Call For Paper: http://vlsi.nj.nec.com/IEEE-Computer
3. ASPLOS-X Early registration deadline for ASPLOS-X has been extended to
September 11
Submitted by Luiz Barroso <luiz@google.com>
Call for Participation http://www.cs.wisc.edu/asplos-X/
4. Workshop on Parallel I/O in Cluster Computing and Computational Grids
Submitted by Jemal Abawajy <abawjem@scs.carleton.ca>
CALL FOR PAPERS www.scs.carleton.ca/~abawjem/ccgrid03/gridcc03.html
5. Workshops Held in conjunction with HPCA 9
2nd Annual Workshop on Novel Uses of System Area Networks
http://www.csl.cornell.edu/SAN-2
Workshop on Network Processors:
http://www.cs.washington.edu/NP2
6. Workshops Held in Conjunction with MICRO-35.
Submitted by Daniel.Connors@Colorado.EDU
CALL FOR PAPERS: http://www.microarch.org/micro35
send an email to
qyang@ele.uri.edu
http://hopper.computer.org/correspo.nsf/signup?OpenForm
Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Dear colleague,
I invite you to submit your work and participate in the newly-founded Workshop on Application Specific Processors. Best regards,
Alex Orailoglu, Program Chair
CALL FOR PAPERS
First WORKSHOP ON APPLICATION SPECIFIC PROCESSORS (WASP'02)
http://dna.ucsd.edu/wasp1
To be held in conjunction with MICRO-35
November 19th, 2002
Hilton Hotel, Istanbul, Turkey
THE DEADLINE FOR SUBMISSIONS IS September 11th (+ automatic 1 week extension)
The workshop papers explore (micro)architectural design approaches and tradeoffs and compiler technologies, for both domain-specific and customizable emb edded processors. The workshop aims at generating a forum wherein the various approaches to address the twin challenges of cost amortization over large volumes while delivering optimal cost, performance, and power characteristics for a wide segment of embedded processor market niches will be explored and compared. WASP explores emerging trends and novel concepts in applicationspecific processors. Major topics include, but are not limited to:
THE DEADLINE FOR SUBMISSIONS IS September 11th, 2002. There is an automatic, one week extension for late papers. There will be no other extensions.
Submit one electronic copy of a paper in PDF format. The paper should not exceed 8 pages. Please visit the website for paper format guidelines and submission instructions. Notification of acceptance will occur by October 5, 2002.
Program Chair:
Alex Orailoglu, UC San Diego, USA
Program committee members:
(to include)
Brad Calder, UC San Diego
Apostolos Dollas, Tech U of Crete
Nikil Dutt, UC Irvine
Masaharu Imai, Osaka U.
Scott Mahlke, U Michigan
Peter Marwedel, U Dortmund
Trevor Mudge, U Michigan
Peter Petrov, UC San Diego
Stamatis Vassiliadis, Delft U.
Alex Veidenbaum, UC Irvine
Hiroto Yasuura, Kyushu U.
Call For Papers
IEEE Computer Magazine Special Issue on "Hardware/Software Co-Design: Techniques,
Tools and Architectures"
Guest Editors:
Joerg Henkel, NEC USA Inc (henkel@nec-lab.com)
Xiaobo Sharon Hu, Univ. of Notre Dame (shu@cse.nd.edu) Shuvra S. Bhattacharyya, Univ. of Maryland (ssb@eng.umd.edu)
Important Dates:
-- deadline for submission: October 15th 2002
-- publication date: April 2003
Through a decade of intense research, Hardware/Software CoDesign has become an integral part in the design process of embedded systems. The advent of hardware/software co-design techniques has facilitated shorter time to markets, reduced system costs and increased functionality and complexity for many of today’s embedded system’s designs. However, as the demand for more complex, faster, lighter and cooler embedded systems is ever increasing, the co-design field is facing even bigger challenges.
It can be observed particularly that the design of mobile devices (such as personal digital assistants, cell phones, digital cameras etc.) will impose a large number of challenging hurdles in the future: a) an increasing complexity of these SOC designs due to their increased functionality (handwriting recognition, speech recognition, video and image processing, PC-tools and OS compatibilities etc), b) a large number of tight and in part contradictory design constraints (like high performance, low power consumption, small chip area, ease of testability etc.), c) an increasing pressure for time-to-market. Additionally, increasing time-to-market pressures place new demands on design flexibility and the role of software.
The goal of this special issue is to publish cutting edge research in hardware/software co-design techniques, tools and architectures that are aimed at providing novel solutions for the design process of complex embedded systems such as mobile devices, but are not limited to:
Computer-aided Co-design Techniques: specification and
modeling, synthesis, partitioning, estimation, platform-
based design, design space exploration, co-simulation, test
strategies
Software for Co-design: code generation, software
development environments, RTOS, process scheduling, system
integration, communication protocols
Co-design Architectures: hardware/software interfaces,
distributed and multiprocessor architectures, re-
configurable architectures
Submission Requirements: Authors are invited to submit their original, previously unpublished work (not currently submitted for review elsewhere) in English in PDF file format. The paper length in double-spaced, 12 point, 8.5"x11" format must not exceed 20 pages including figures, tables, references etc. Each submission should contain a) a cover page with author contact information (names, affiliations addresses, phone numbers, fax numbers, email addresses), b) an abstract of 100 words and c) the paper body as described above. It is required that submitted manuscripts are cleared for publication. Accepted manuscripts will be edited for technical content, structure, style, clarity, and grammar. For further information please contact the guest editors or check
http://vlsi.nj.nec.com/IEEE-Computer and
http://computer.org/computer/author.htm#submitting
Important Dates:
-- deadline for submission: October 15th 2002
-- publication date: April 2003
Early registration deadline for ASPLOS-X has been extended until this coming Wednesday, September 11.
Please register before this date for lower conference, tutorial, and workshop rates. You can do so at:
http://www.cs.wisc.edu/asplos-X/
This Bay Area edition of ASPLOS takes place Oct. 5-9, 2002, in San Jose, CA.
ASPLOS, the International Conference on Architectural Support for Programming Languages and Operating Systems, is the premier multi-disciplinary systems conference. It has captured some of the major computer systems innovations of the past 15 years, including RAID and network-storage, clusters and networks-of-workstations, compiler optimizations, small and large-scale multiprocessors, operating systems, RISC and VLIW processors.
Take advantage of this unique biennial gathering of some of the top systems researchers and professionals from multiple areas of computer sciences.
--Luiz Barroso, ASPLOS-X Publicity Chair.
Dear Friends:
Please find enclosed call for papers of upcoming Workshop on Parallel
I/O
in Cluster Computing and Computational Grids to be held in conjunction
with
3rd IEEE/ACM International Symposium on Cluster Computing and the Grid
(CCGrid 2003)
Tokyo, Japan.
We appreciate if you can also share the CFP with your colleagues working
in cluster and grid computing.
for more information, please check the following link:
http://www.scs.carleton.ca/~abawjem/ccgrid03/gridcc03.html
Thanks
J.H. Abawajy
Call for Papers and Participations
The growing popularity of the Internet along with the availability of powerful
computers and high-speed networks as low-cost commodity components are
changing the way we do computing. Two advanced computing themes have
emerged: "cluster computing" and "global network computing" (grid computing).
The aim of the workshop is to address parallel I/O related problems on Cluster
Computing and Computational Grids by bringing together international cluster
and network-based computing researchers, developers, and users. The workshop
will also serve as a forum to present the latest work, and highlight related
activities from around the world.
We are soliciting high quality papers reporting original work on parallel I/O
in Cluster Computing and Computational Grids in both theoretical and
experimental research on a broad range of topics, including, but not limited
to:
File Systems and Parallel I/O for clusters;
Data Distribution and Load Balancing in the presence of I/O Operations;
Tools for Operating and Managing I/O Operations;
Novel Hardware and Software I/O Architectures;
Parallel Disk Models and Algorithms;
Experiences with Massive Data Sets;
I/O Performance Analysis;
Drivers and Application Programming Interfaces;
Advances in Storage Technology;
Compilers Techniques for High Performance I/O Operations;
Language and runtime libraries;
Parallel I/O support for databases.
All queries may be directed to the PC chair:
Jemal H. Abawajy
Voice: (613) 520-2600 ext.1035
FAX: (613) 520-4334
abawjem@scs.carleton.ca
Program Committee Members
Rajeev Thakur
Mathematics and Computer Science Division
Argonne National Laboratory
thakur@mcs.anl.gov
Toni Cortes
Barcelona School of Informatics (FIB)
Universitat Politecnica de Catalunya (UPC)
http://people.ac.upc.es/toni/
toni@fib.upc.es
Yiming Hu
Dept. of Electrical & Computer
Engineering & Computer Science
University of Cincinnati
http://www.ececs.uc.edu/~yhu/
yhu@ececs.uc.edu
Heinz Stokinger
Research Fellow in Computer Science
European DataGrid project
http://hst.home.cern.ch/hst/cv.html
Peter Brezany
University of Vienna
Institute for Software Science
http://www.par.univie.ac.at/~brezany/
brezany@par.univie.ac.at
Erich Schikuta
Institute of Applied Computer Science and Information Systems, Department of
Data Engineering
University of Vienna,
http://www.pri.univie.ac.at/~schiki/
schiki@ifs.univie.ac.at
Alok Choudhary
Northwestern University
http://www.ece.nwu.edu/~choudhar/
choudhar@ece.nwu.edu
Robert B. Ross
Argonne National Laboratory
http://www-unix.mcs.anl.gov/~rross/resume.htm
rross@mcs.anl.gov
Evgenia Smirni
College of William and Mary
http://www.cs.wm.edu/~esmirni
esmirni@cs.wm.edu
Jemal H. Abawajy
Centre for Parallel and Distributed Computing
School of Computer Science
http://www.scs.carleton.ca/~abawjem
abawjem@scs.carleton.ca
2nd Annual Workshop on Novel Uses of System Area Networks
(SAN-2)
February 9, 2003
Held in conjunction with HPCA-9
The 9th International Symposium on High Performance Computer Architecture
February 8-12, 2003
Anaheim, CA
HOME PAGE
http://www.csl.cornell.edu/SAN-2/
OVERVIEW
This one-day workshop will focus on innovative uses of emerging network technology for system area networks (SANs) and intelligent system area components (NICs, switches, disks, node controllers, etc.). As the price of individual cluster components continues to fall, and their performance steadily improves, clusters of PCs or workstations are becoming commonplace in areas once reserved for supercomputers or massively parallel architectures. The networks used in clusters have moved from traditional Ethernet to system area networks, such as the Virtual Interface Architecture, Myrinet, ServerNet, and the forthcoming InfiniBand and 3GIO (PCI Express) networks. System area networks are characterized by high bandwidth; low latency; a switched network environment; reliable transport service implemented directly in hardware; no kernel intervention to send and receive messages; and little or no copying on either the sending or receiving side. SANs may be used for enterprise applications such as databases, web servers, reservation systems, and parallel computing environments. The SAN-2 workshop will include presentations of accepted technical papers from both industry and academia and a keynote address by a speaker yet to be determined.
TOPICS
This workshop will focus on non-traditional uses of commodity system area networks, intelligent SAN components, and innovative system area network architectures. Topics of interest include, but are not limited to, the following:
Intelligent system area components (NICs, switches, disks, node controllers, etc.)
SAN architecture enhancements
Clustering middleware that takes advantage of SAN hardware
Fault-tolerant SAN solutions
SAN-based shared memory architectures
Novel message-passing library implementations
Active I/O or Active Networking systems leveraging SAN architectures
Use of remote memory operations in SANs
Novel uses of SAN-based cluster architectures
Compilation support for SANs
Applications for clusters using SANs
IMPORTANT DATES
Submission Deadline: November 30, 2002
Notification to Authors: December 21, 2002
Final Papers Due: January 14, 2003
SUBMISSIONS
Authors should submit an extended abstract no longer than 5 pages for consideration. Reviews of all papers will be blind. Accepted papers must be no longer than 12 single-spaced pages (including figures, references, and appendices) using 12pt font. Submit one electronic copy of the abstract in PDF format via email to SAN2WORKSHOP@csl.cornell.edu by November 30.
Notification of acceptance will be given by December 21, and camera-ready papers will be due January 14. All accepted papers will be presented at the workshop and included in a bound proceedings that will be distributed at the workshop. Authors should use IEEE TOC format guidelines for final submissions. In addition, accepted papers will be made available on this site.
PROGRAM COMMITTEE
Ricardo Bianchini, Rutgers University
Angelos Bilas, University of Toronto
Mark Heinrich, Cornell University
Pankaj Mehra, Hewlett Packard
Li-Shiuan Peh, Princeton University
Evan Speight, Cornell University
Craig Stunkel, IBM Research
PRELIMINARY CALL FOR PAPERS
Workshop on Network Processors
http://www.cs.washington.edu/NP2/
Anaheim, California
February 9, 2003
Held in conjunction with HPCA 9 - The 9th International
Symposium on High-Performance Computer Architecture
http://www.cs.arizona.edu/hpca9/
February 8-12, 2003
OVERVIEW
As the performance and importance of digital communication networks have increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility and economy requirements, the networking industry has opted to build products around network processors. These processors are programmable yet application-specific; their designs are tailored to efficiently implement communications applications such as: routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. The term network processor is used here in the most generic sense -- from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors.
Network processor design is an emerging field with numerous challenges and opportunities. The goal of this workshop is to provide a forum for engineers and scientists from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. We are especially interested in attracting new or experimental techniques and approaches.
IMPORTANT DATES
Papers due : November 1, 2002
Notification to authors : January 6, 2003
TOPICS
Topics of particular interest include, but are not limited to:
The workshop will consist of a keynote address, paper presentations and a panel session. In addition to academic and research contributions, product descriptions that focus on architecture (hardware or software) or performance analysis will also be considered. Attendees will receive a copy of workshop papers. After the workshop, selected papers will be published in a book entitled Network Processor Design: Issues and Practices Volume II (Morgan Kaufman Publishers).
SUBMISSIONS
Please submit full papers (single spaced, font size 11, 1 inch margins, not exceeding 15 pages) in Adobe PDF format for review to pcrowley@cs.washington.edu.
NOTES FROM NP1 (2002):
Selected papers from NP1 and additional industry contributions will appear in Network Processor Design : Issues and Practices Volume I (Morgan Kaufmann Publishers, September 2002).
ORGANIZERS
Patrick Crowley, University of Washington (pcrowley@cs.washington.edu) Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu) Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu) Peter Z. Onufryk, IDT (peter.onufryk@idt.com)
MICRO-35 Call for Papers
The 35th International IEEE/ACM Symposium on Microarchitecture
Istanbul, Turkey, Nov. 18-22, 2002
The MICRO organizing committee is pleased to announce that the 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-35) will be held in Istanbul, Turkey from Nov. 18 to Nov. 22, 2002. MICRO represents the premier technical forum on microarchitecture. MICRO is the best scientific venue to meet the key people in the microprocessors field; it is well attended by both academic and industrial experts on the design of microprocessors.
MICRO-35 will feature outstanding keynote speeches by Tilak Agerwala (Vice President, Systems, IBM Research) and by Justin Rattner (Intel Fellow and Director, Microprocessor Research, Intel Labs). The MICRO-35 technical program will be of very high quality, as usual: This year, we have had 150 papers submitted to MICRO (another record for MICRO), out of which 36 were accepted. MICRO-35 will include 6 tutorials on exciting topics of current interest: aynchronous and partially asynchronous microprocessor design, thermal management in microprocessors, compilation for the Itanium, network processors, and microarchitecture simulation tools. There will also be 4 cutting-edge workshops, on EPIC architectures and compilers, media and stream processors, multithreading, and application-specific processors.
Advance program:
http://www.microarch.org/micro35/advance_program.html
Tutorials (http://www.microarch.org/micro35/tutorials.html)
Asynchronous Microprocessor Design
Tutorial on Partially Asynchronous Microprocessors (PAMs)
Thermal Management Issues for Microprocessors
An Introduction to Network Processor Research and Design
Open Research Compiler (ORC) 2.0 -Tuning Performance on Itanium
Simics Microarchitect's Toolset
Workshops (http://www.microarch.org/micro35/workshops.html)
6th Workshop on Multi-threaded Execution, Arch, and Compilation 4th Workshop on Media and Stream Processors 2nd Workshop on EPIC Architectures and Compiler Technology 1st Workshop on Application Specific Processors (WASP)
I especially encourage students to attend MICRO-35, and to submit papers to the MICRO-35 workshops. We have created a new Student Advocate position this year in MICRO, for making sure we are providing the right opportunities for the students, who will become the next generation of researchers in our field. Due to generous corporate donations and support from the National Science Foundation, we will be able to offer many travel grants for students and junior faculty. There will also be best student paper and best student presentation awards in MICRO-35's technical programs. ACM and IEEE CS have graciously agreed to provide free memberships to the award-winning student authors.
Student/Junior Faculty travel grants:
http://www.microarch.org/micro35/grants/
Istanbul is a jewel of a city, combining the magnificent historical treasures of past civilizations with the life of a modern metropolis. Besides the architectural marvels of St. Sophia and the Blue Mosque, Istanbul's rich cultural heritage offers countless Roman, Byzantine, and Ottoman historical sites. The old bazaars, cafes, restaurants, night clubs, and shopping centers add to Istanbul's colorful daily life taking place on both the European and Asian sides of the blue waters of the Bosphorus strait, and on the pretty Islands nearby. Please take a look at the Istanbul photo gallery on our Web site. Our social program at MICRO-35 will try to give you a glimpse of the cultural richness of Istanbul. After the conference, I would encourage you to stay in Istanbul a few days to see more, and/or visit other interesting places in Turkey, such as the Antalya or Izmir regions. MICRO-35's official conference organization/travel agency in Istanbul, SEMOR, will offer a portfolio of organized tours/travel packages to interested MICRO-35 attendees.
Pictures of Istanbul:
http://www.microarch.org/micro35/istanbul_photo_gallery.html
MICRO-35 will take place at the Istanbul Hilton, an established high-end hotel in Istanbul. We are glad to say that MICRO-35 is able to offer low rates to the attendees at this hotel. But I would suggest making your hotel reservations early; space is limited.
Hotel Registration:
https://form.garanti.com.tr/genel/html/micro_reg-v1.1.htm
Conference Registration:
https://turing.acm.org/sigs/sigmicro/micro35/
If you have any questions or comments about MICRO-35, please feel free to contact me at: kemal@watson.ibm.com.
Kemal Ebcioglu
Micro-35 General Chair
IBM T.J. Watson Research Center
For more information, please refer to out conference web site http://www.microarch.org/micro35. Thank you for your time in reading this message.