A Technique to Reduce Chip Area Cost of On-chip Caches
Warning! Under constructing....
We present a technique for minimizing chip-area cost of implementing
an on-chip cache memory of microprocessors.
The main idea of the technique is Caching Address Tags, or CAT cache for short.
The CAT cache exploits locality property that exists among addresses of
memory references for the purpose of minimizing chip area-cost of address tags.
By keeping only a limited number of distinct tags of cached data
rather than having as many tags as cache lines,
the CAT cache can reduce the cost of implementing tag memory by an order of magnitude
without noticeable performance difference from ordinary caches.
Therefore, CAT represents another level of caching for cache memories.
Simulation experiments are carried out to evaluate performance of CAT cache as compared
to existing caches.
Performance results of SPEC92 programs show that the CAT cache
with only a few tag entries
performs as well as ordinary caches while chip-area saving is significant.
Such area saving will increase as the address space of a processor increases.
By allocating the saved chip area for larger cache capacity, or more powerful
CAT is expected to have a great impact on overall system performance.
To download the full paper in ps format
(Over 1.2 MBytes compressed)
To read the full paper in pdf format
IEEE-Copyrighted material: Personal use of this material is permitted.
However, permission to reprint/republish this material for advertising or
promotional purposes or for creating new collective works for resale or
redistribution to servers or lists, or to reuse any copyrighted component of
this work in other works must be obtained from the IEEE.
CAT is sponsored by National Science Fundation.
Here are related Conference presentations
and related journal publications for the CAT project.
Return to HPCL home page...