Fourth Annual Boston Area Architecture Workshop
Advance Program

University of Rhode Island
University Club, Rhode Island Room

February 3, 2006


10:00am-10:25am: Continental Breakfast

10:25am-10:30am: Welcome by Dean Bahram Nassersharif, URI College of Engineering, & the Wkshp. Organizers

10:30am-11:30am: Session 1, Temperature, Power and Energy
(Session Chair: David Kaeli, Northeastern University)

Fast Transient Thermal Simulation Based on Linear System Theory,
Yongkui Han, Israel Koren and C. Mani Krishnaa, UMass, Amherst
Impact of Process Variations on Low Power Cache Design,
Mahmoud Bennaser and Csaba Andras Moritz, UMass, Amherst
Compiler-Based Adaptive Fetch Throttling for Energy Efficiency,
Huaping Wang, Yao Guo, Israel Koren and C. Mani Krishna, UMass, Amherst
Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks,
Tali Moreshet, R. Iris Bahar and Maurice Herlihy, Brown University

11:30am-11:45am: Short Break

11:45am-12:45pm: Session 2, Architectures and Performance
(Session Chair: C. Andras Moritz, University of Massachusetts, Amherst)

Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems,
Ayse Yilmazer, URI; Resit Sendag, URI; Joshua J. Yi, Freescale Semiconductor; and Augustus K. Uht, URI
Using R-STAGE to Optimize the DASAT Cache System,
M. Tyler Maxwell, Charles C. Weems, J. Eliot B. Moss and Robert B. Moll, UMass, Amherst
Exploring Architectural Challenges in Scalable Underwater Wireless Sensor Networks,
Z. Jerry Shi and Yunsi Fei, University of Connecticut
ILP is Dead, Long Live IPC!,
Gus Uht, URI

12:45pm-1:30pm: Sandwich Buffet Lunch

1:30pm-2:30pm: Keypanel Session, 'Whence Goeth the Microprocessor?' (Moderator: Gus Uht)

Constituencies and Keypanelists:
* Academia: Prof. Anant Agarwal, Professor of Electrical Engineering and Computer Science, MIT.
* End Users: Dr. Atul Chhabra, Enterprise Architect and Senior IT Manager, Verizon, Inc.
* Industry: Dr. Joel Emer, Fellow, Intel Corp.
* Everybody: The Audience, various positions, many institutions.

2:30pm-3:00pm: Long Break

3:00pm-4:00pm: Session 3, Simulation and Design (Session Chair: Qing Yang, University of Rhode Island)

Branch Trace Compression for Snapshot-Based Simulation,
Kenneth C. Barr and Krste Asanovic, MIT
Requirements for any HPC/FPGA Application Development Tool Flow
(that gets more than a small fraction of potential performance)
Martin Herbordt, Tom VanCourt and Yongfeng Gu, Boston University
Accelerating Architectural Exploration Using Canonical Instruction Segments,
Rose F. Liu and Krste Asanovic, MIT
Tortola: Addressing Tomorrow's Computing Challenges through Hardware/Software Symbiosis,
Kim Hazelwood, University of Virginia and Intel Massachusetts

4:00pm-4:15pm: Short Break

4:15pm-5:15pm: Session 4, Dependability (Session Chair: R. Iris Bahar, Brown University)

PRINS: Optimizing Performance of Reliable Internet Storages,
Weijun Xiao, Jin Ren and Qing Yang, URI
Failure Detection in Programmable Network Processors,
Yizheng Zhou, Vijay Lakamraju, Israel Koren and C.M. Krishna, UMass, Amherst
Software Fault Detection Using Dynamic Instrumentation
George A. Reis and David I. August, Princeton University; and
Robert Cohn and Shubhendu S. Mukherjee, Intel Massachusetts
Self-healing Nanoscale Architectures on 2-D Nano-fabrics
Teng Wang, Mahmoud Ben Naser, Yao Guo and Csaba Andras Moritz, UMass, Amherst

5:15pm-5:45pm: Long Break

5:45pm-6:30pm: Session 5, Emerging Concepts (Session Chair: Martin Herbordt, Boston University)

Functional Programming in Embedded System Design,
Al Strelzoff, E-TrolZ, Inc.
The Fresh Breeze Memory Hierarchy,
Jack B. Dennis, MIT
Ideal and Resistive Nanowire Decoders: General Models for Nanowire Addressing,
Eric Rachlin and John E. Savage, Brown University

6:30pm-6:35pm: Closing Remarks