Welcome to IEEE TCCA Email-Monthly, March 2005.
*June 4, 2005, Madison, Wisconsin, in conjunction with the 32nd ISCA *SUBMISSION DEADLINE: March 28, 2005 *Submitted by: Joshua J Yi <jjyi@ece.umn.edu> *CALL FOR PAPERS http://www.arctic.umn.edu/MoBS
and Software *March 20-22, 2005, Austin, Texas *Registration: http://ispass.org *Submitted by: "Bondi, Jim" <bondi@ti.com>
Communications Systems *October 26-28, 2005, Princeton, New Jersey, USA *SUBMISSION DEADLINE: May 9, 2005 at 11:59PM PST *Submitted by: Greg Byrd <gbyrd@ncsu.edu> *CALL FOR PAPERS: http://www.ancsconf.org
*October 24 - 26, 2005, Singapore *SUBMISSION DEADLINE: May 15, 2005 *Submitted by: Ron Oldfield <raoldfi@SANDIA.GOV> *CALL FOR PAPERS http://www.acsac05.ntu.edu.sg/
Compilation Techniques *Saint Louis, Missouri, September 17-21, 2005 *SUBMISSION DEADLINE: March 23rd, 2005 *Submitted by: <milos.prvulovic@cc.gatech.edu> *CALL FOR PAPERS http://www.pactconf.org/pact05
*Sunday, June 5, 2005, Held in conjunction with ISCA-32, Madison, WI *Submission deadline: April 4, 2005 *Submitted by: Kevin Skadron <skadron@cs.virginia.edu>
send an email to
qyang@ele.uri.edu
* To subscribe to this mailing list, please sign up at <http://www.computer.org/TCsignup/index.htm>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* http://www.arctic.umn.edu/MoBS * * *
Held in conjunction with the 32nd Annual International Symposium on Computer Architecture
Madison, Wisconsin
June 4, 2005
The primary goals of this workshop are to accelerate the development of simulation technologies that are necessary to support the research of future generation architectures and to encourage the advancement of under-researched. areas related to computer architecture measurement, such as modeling, benchmark implementation and benchmark suite construction, and formal methods of design space exploration and performance analysis.
Topics of interest include, but are not limited to:
Notification Date: May 4, 2005 Final Version Due: May 18, 2005 Workshop Date: June 4, 2005
Lieven Eeckhout Ghent University leeckhou@elis.ugent.be Joshua J. Yi Freescale Semiconductor jjyi@ece.umn.edu
David I. August Princeton University Pradip Bose IBM Research T.J. Watson Brad Calder University of California, San Diego Lizy Kurian John University of Texas at Austin David J. Lilja University of Minnesota at Twin Cities Peter Magnusson Virtutech Jim Smith University of Wisconsin -- Madison
CALL FOR PARTICIPATION
International Symposium on Performance Analysis of Systems and Software
(ISPASS-2005)
March 20-22, 2005
Austin, Texas
Join us at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005). ISPASS provides a forum for sharing advanced academic and industrial R&D work focused on performance analysis in the design of computer systems and software. Keynote talks will feature Marcus Levy of EEMBC on benchmarking embedded processors and Tom Conte of North Carolina State University on getting insight from performance data.
A workshop on Unique Chips and Systems (UCAS) will be held on Sunday before the main symposium starts. UCAS will bring together researchers and practitioners in many areas of chip and system design. UCAS will feature a keynote by Peter Hofstee of IBM on the new CELL processor.
The ISPASS advanced program is shown immediately below.
For detailed information on symposium/workshop registration and hotel reservations, please refer to http://ispass.org .
Schedule
Sunday, March 20
8:30am-5:00pm UCAS: Workshop on Unique Chips and Systems
Monday, March 21 - ISPASS Symposium, Day 1
8:45- 9:00 Welcome
9:00-10:00 Keynote talk #1: EEMBC and the Purposes of
Embedded Processor Benchmarking
10:00-10:30 Break
10:30-12:00 Session #1: Benchmarking
12:00- 1:30 Lunch
1:30- 3:00 Session #2: Power and Thermal Management
3:00- 3:30 Break
3:30- 5:00 Session #3: Accelerating Simulation
5:00- 6:30 Panel discussion: Architectures for the Future
Tuesday, March 22 - ISPASS Symposium, Day 2
9:00-10:00 Keynote talk #2: Insight, Not (Random) Numbers 10:00-10:30 Break 10:30-12:00 Session #4 (Rm A): Multithreading 10:30-12:00 Session #5 (Rm B): Statistical and Trace-Driven Simulation 12:00- 1:30 Lunch 1:30- 3:00 Session #6 (Rm A): Data Parallel Processing 1:30- 3:00 Session #7 (Rm B): Network Processing 3:00- 3:30 Break 3:30- 5:00 Session #8 (Rm A): Performance & Workload Characterization 3:30- 5:00 Session #9 (Rm B): Communication and Reliability
Detailed Program
Keynote talk #1: EEMBC and the Purposes of Embedded Processor Benchmarking Markus Levy, EEMBC
Session 1: Benchmarking
Session chair: David Kaeli, Northeastern University
BioBench: A Benchmark Suite of Bioinformatics Applications,
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce Jacob,
Chau-Wen Tseng, Donald Yeung
University of Maryland, College Park
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout (Ghent), Lizy K. John The University of Texas at Austin
Simulation Differences Between Academia and Industry: A Branch Prediction
Case Study,
Gabriel H. Loh
Georgia Institute of Technology
Session 2: Power and Thermal Management Session chair: Jim Bondi, Texas Instruments
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application
Specific Instruction Set Synthesis
Allen C. Cheng, Gary S. Tyson (Florida State), Trevor N. Mudge
The University of Michigan
A High Performance, Energy Efficient GALS Processor Microarchitecture with
Reduced Implementation Complexity
YongKang Zhu, David H. Albonesi (Cornell),
Alper Buyuktosunoglu (IBM T.J. Watson)
University of Rochester
Studying Thermal Management for Graphics-Processor Architectures Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke The University of Virginia
Session 3: Accelerating Simulation
Session chair: Sangyeun Cho, University of Pittsburgh
Accelerating Multiprocessor Simulation with a Memory Timestamp Record Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovic MIT
Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time
Through Binary Modification,
Jeff Ringenberg, Chris Pelosi, David Oehmke, Trevor Mudge
The University of Michigan
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair
Comparison
Magnus Ekman, Per Stenstrom
Chalmers University of Technology
Panel discussion: Architectures for the Future
Moderator: Erik Altman, IBM T. J. Watson Research Center
Panelists:
Doug Burger, The University of Texas at Austin
Roy Ju, Intel
Ravi Nair, IBM T.J. Watson Research Center
Kunle Olukotun, Stanford University
Eric Rotenberg, North Carolina State University
Keynote talk #2: Insight, Not (Random) Numbers Tom Conte, North Carolina State University
Session 4: Multithreading
Session chair: David Christie, AMD
Performance Characterization of Java Applications on SMT Processors Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang Iowa State University
Partitioning Multi-Threaded Processors with a Large Number of Threads Ali El-Moursy, Rajeev Garg, David H. Albonesi (Cornell), Sandhya Dwarkadas University of Rochester
Power-Performance Implications of Thread-level Parallelism on
Chip Multiprocessors
Jian Li, Jose F. Martinez
Cornell University
Session 5: Statistical and Trace-Driven Simulation Session chair: Charles Lefurgy, IBM
Motivation for Variable Length Intervals and Hierarchical Phase Behavior Jeremy Lau, Erez Perelman, Greg Hamerly (Baylor), Timothy Sherwood (UC-Santa Barbara), Brad Calder University of California, San Diego
Fast, Accurate Microarchitecture Simulation Using Statistical
Phase Detection
Ram Srinivasan, Jeanine Cook, Shaun Cooper
New Mexico State University
A Trace-Driven Simulator For Palm OS Devices Hyrum Carroll, J. Kelly Flanagan, Satish Baniya Brigham Young University
Session 6: Data Parallel Processing
Session chair: Lieven Eeckhout, Ghent University (Belgium)
On the Scalability of 1- and 2-Dimensional SIMD Extensions for
Multimedia Applications
Friman Sanchez, Mauricio Alvarez, Esther Salami, Alex Ramirez, Mateo Valero
Universitat Politecnicade Catalunya
Dataflow: A Complement to Superscalar, Mihai Budiu (Microsoft), Pedro V. Artigas, Seth Copen Goldstein Carnegie Mellon University
Scalarization on Short Vector Machines
Yuan Zhao, Ken Kennedy
Rice University
Session 7: Network Processing
Session chair: Rema Hariharan, Sun Microsystems
Anatomy and Performance of SSL Processing Li Zhao, Ravi Iyer (Intel), Srihari Makineni (Intel), Laxmi Bhuyan University of California, Riverside
Architectural Characterization of Processor Affinity in Network Processing
Annie Foong, Jason Fung, Don Newell, Seth Abraham, Peggy Irelan,
Alex Lopez-Estrada
Intel Corporation
Performance Analysis of a New Packet Trace Compressor based on
TCP Flow Clustering
Raimir Holanda, Javier Verdu, Jorge Garcia, Mateo Valero
Technical University of Catalonia
Session 8: Performance and Workload Characterization Session chair: David Albonesi, Cornell University
Analysis of Network Processing Workloads Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf University of Massachusetts
The Strong Correlation Between Code Signatures and Performance Jeremy Lau, Jack Sampson, Erez Perelman, Greg Hamerly, Brad Calder University of California, San Diego
Pro-active Page Replacement for Scientific Applications: A Characterization
Murali Vilayannur, Anand Sivasubramaniam, Mahmut Kandemir Pennsylvania State University
Session 9: Communication and Reliability Session chair: David Murrell, IBM
Reaping the Benefit of Temporal Silence to Improve
Communication Performance
Kevin M. Lepak, Mikko H. Lipasti
University of Wisconsin
Balancing Performance and Reliability in the Memory Hierarchy Ghazanfar-Hossein Asadi, Vilas Sridharan, Mehdi B. Tahoori, David Kaeli Northeastern University
On the Provision of Prioritization and Soft QoS in Dynamically Reconfigurable Shared Data-Centers over InfiniBand P. Balaji, S. Narravula, K. Vaidyanathan, H.-W. Jin, D. K. Panda The Ohio State University
Keynote and panel details
Keynote talk #1:
EEMBC and the Purposes of Embedded Processor Benchmarking
Markus Levy, EEMBC
Abstract:
Embedded processor benchmarking serves many purposes, from providing
a framework to guide architectural choices in the development
stage to giving original equipment manufacturers an objective
means of predicting processor performance in specific application
scenarios. Creating embedded processor benchmarks is a comparatively
simple task. More difficult is winning acceptance from the diverse
audiences who could be expected to rely on them. The Embedded
Microprocessor Consortium (EEMBC), now in its seventh year,
represents a model that has succeeded relatively well in both
tasks. In this presentation, I will describe the structure of
EEMBC in its technical and political aspects, review its accomplishments
since 1997 in developing various benchmark suites, and discuss
the application of various metrics (such as architectural efficiency,
power consumption, bus speed, and cache size) beyond raw performance
in evaluating the suitability of a given processor for a particular
application or system.
Biographical sketch:
Markus Levy is founder and president of EEMBC, the Embedded Microprocessor
Benchmark Consortium. Markus has more than nine years of experience
working with EDN Magazine and Instat/MDR, and is a very seasoned editor and
analyst with a proven record of processor and development tool analysis,
article writing, and the delivery of countless technical seminars.
Beginning in 1987, Markus worked for Intel Corporation as both a senior
applications engineer and customer training specialist for Intel's
microprocessor and flash memory products. While at Intel, Markus received
several patents for his ideas related to flash memory architecture and
usage as a disk drive alternative. Markus is also co-author of "Designing
with Flash Memory", the only technical book on this subject.
Panel discussion
More than a decade ago claims were made that "Architecture is dead." Since then we have gone through several Moore's Law generations, and a variety of new ISA proposals and implementations (e.g. Itanium, Java, Niagara, TRIPS, Slipstream) and ISA extensions, particularly for SIMD. What does the future hold?
The panelists will debate each other and the audience about these and related issues.
Keynote talk #2
Insight, not (random) numbers
Tom Conte, North Carolina State University
Abstract:
Hamming said "The purpose of computing is insight, not numbers," yet
this conference, like many today, is awash only in numbers. These
numbers are perhaps more strategic than insightful. The numbers are used
by designers, who want to prove their invention is better than the
status quo. Then there are marketers, who want to prove their product's
the one to buy over the competition. And then there are the users, who
quite frankly are not getting much insight out of any of this. This talk
will step back and discuss two aspects of insightful computing: who
speaks for the users, and how much we should trust our numbers.
Biographical sketch:
Tom Conte is Professor of Electrical and Computer Engineering and
Director, Center for Embedded Systems Research, at North Carolina State
University. His research is in the areas of microprocessor
architecture, compiler code generation/optimization, and
performance evaluation. Conte is the chair of the IEEE Computer
Society Technical Committee on Microprogramming and Microarchitecture
(TC-uARCH) and a Fellow of the IEEE. He received his Ph.D.
degree in EE from the University of Illinois at Urbana-Champaign in 1992.
Committees and Officers
Rema Hariharan, Sun Microsystems
David Kaeli, Northeastern Univ.
Alvin R. Lebeck, Duke Univ.
Charles Lefurgy, IBM
Zhiyuan Li, Purdue Univ.
Mikko H. Lipasti, Univ. of Wisconsin
Bill Mangione-Smith, UCLA
Vijaykrishnan Narayanan, Penn State Univ.
D.K. Panda, Ohio State Univ.
Gopal Raghavan, Nokia
Resit Sendag, Univ of Rhode Island
Per Stenstrom, Chalmers Univ. (Sweden)
Deepu Talla, Texas Instruments
Mateo Valero, UPC, Barcelona
David Williamson, ARM
1st Symposium on
Architectures for Networking and Communications Systems
ANCS 2005
http://www.ancsconf.org
October 26-28, 2005
Princeton, New Jersey, USA
Sponsored by:
ACM Special Interest Group on Computer Architecture (SIGARCH)
ACM Special Interest Group on Communications (SIGCOMM)
IEEE Computer Society Tech. Committee on Computer Architecture IEEE Communications Society Tech. Committee on Computer Communications
ANCS is new research conference that focuses on the design of the hardware and software components used to create modern communication networks. The combination of increasing network line speeds and expanding functional requirements pose continuing and growing challenges for system designers. New technology elements, including network processors, content addressable memories, configurable logic and special-purpose components offer new opportunities for meeting these challenges, but also raise a variety of new issues. ANCS focuses on architectures for networking and communication in the broad sense, including novel architectures, architectural support for advanced communication, algorithms and protocols for advanced architectures, software and applications for next-generation networking architectures, and methodology and benchmarking for evaluating advanced communication architectures.
Areas of interest include, but are not limited to:
* Network/communications processors
* Intelligent co-processors
* Router architectures
* Switch fabrics/interconnection networks
* Link scheduling, processor/thread scheduling, switch scheduling
* Network adaptors
* Application-specific networks (e.g. SAN)
* Programmable /extensible networks
* Secure communication
* Traffic management
* Packet classification
* Content inspection and filtering
* Energy-efficient designs
We particularly encourage submissions containing highly original ideas. Submissions will be judged on originality, significance, interest, clarity, and correctness.
The PAPER DEADLINE for submissions is May 9, 2005 at 11:59PM PST (US). NO FURTHER EXTENSIONS WILL BE GRANTED. ANCS will use double-blind reviewing, so submitted papers should not include the authors' names. All papers must be submitted electronically, in PDF format for letter-size paper. Submissions must be viewable by Adobe Acrobat Reader (version 5.0 or higher) and should not exceed 7,000 words or 10 pages of conference paper format using 10 pt fonts. Submissions exceeding the required limit will not be reviewed by the program committee. Detailed submission instructions will be available by April 1, 2005 at: http://www.ancsconf.org.
Like other conferences, ANCS requires that papers not be submitted simultaneously to any other conferences or publications, that submissions not be previously published, and that accepted papers not be subsequently published elsewhere.
All submissions will be acknowledged by July 30, 2002. If your submission is not acknowledged by this date, please contact the program chairs promptly at ancsPCchairs@arl.wustl.edu.
Important Dates
Submission deadline: May 9, 2005
Author notification: July 30, 2005
Final camera-ready copy: September 6, 2005
Tutorials
A series of tutorials will be held immediately preceding the symposium. Tutorial proposals will be accepted until June 30, 2005. If you wish to give a tutorial (1/2 or 1 day), email a proposal to the Tutorials Chair (Erik Johnson, Erik.Johnson@intel.com). For tutorials, the proposal must include title, brief description of topics to be covered, and bio of the speakers.
General Chair: Alan Berenbaum, Consultant
Steering Committee:
Alan Berenbaum, Consultant
Patrick Crowley, Washington Univ. at St. Louis
Mark Franklin, Washington Univ. at St. Louis
Haldun Hadimioglu, Polytechnic Univ.
Nick McKeown, Stanford Univ.
Peter Z. Onufryk, IDT
K. K. Ramakrishnan, AT&T Labs
Program Co-Chairs:
Kai Li, Princeton University
Jonathan Turner, Washington University at St. Louis
Program Committee:
Andrew Campbell, Columbia Univ.
Patrick Crowley, Washington Univ. at St. Louis
Cezary Dubnicki, NEC
Hans Eberle, Sun Microsystems
Dirk Grunwald, Univ. Of Colorado
Roch Querin, Univ. of Pennsylvania
T.V. Lakshman, Bell Labs
Dan Lenoski, Cisco Systems
Bill Mangione-Smith, UCLA
Kenneth McKenzie, Georgia Tech.
Nick McKeown, Stanford Univ.
Peter Onufryk, IDT
Li-Shuian Peh, Princeton Univ.
Mohammad Peyravian, IBM
Henning Schulzrinne, Columbia Univ.
Steve Scott, Cray
Dimitrious Stiliadis, Bell Labs
Ion Stoica, UC Berkeley
Chuck Thacker, Microsoft
Harrick Vin, UT Austin
Tilman Wolf, UM Amherst
Raj Yavatkar, Intel
Hui Zhang, CMU
CALL FOR PAPERS
Tenth Asia-Pacific Computer Systems Architecture Conference
(ACSAC'05)
Singapore, October 24 - 26, 2005
http://www.acsac05.ntu.edu.sg/
The Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC'2005) will be held in Singapore, during October 24-26, 2005. Authors are invited to submit full papers on all aspects of computer systems architecture, including (but not limited to) the following:
Submissions of Full Papers: 15 May, 2005
Author Notification: 15 July, 2005
Camera-Ready Papers: 7 August, 2005
Registration of One Author: 7 August, 2005
Leedham Graham, Nanyang Tech. Univ., Singapore
T. Srikanthan, Nanyang Tech. Univ., Singapore Jingling. Xue, Univ. of New South Wales, Australia
Vijayan Asari, Old Dominion Univ., USA
Eduard Ayguade, UPC, Spain
Sangyeun Cho, Univ. of Pittsburgh, USA
Lynn Choi, Korea Univ., Korea
Christopher Clarke, The Univ. of Bath, UK
Oliver Diessel, Univ. of New South Wales, Australia
Jean-Luc Gaudiot, Univ. of California Irvine, USA
James Goodman, Univ. of Auckland, New Zealand
Gernot Heiser, National ICT, Australia
Lim Hock Beng, National Univ. of Singapore, Singapore
Wei-Chung Hsu, Univ. of Minnesota, USA
Chris Jesshope, Univ. Van Amsterdam, Netherlands
Hong Jiang, Univ. of Nebraska-Lincoln, USA
Sridharan. K, Indian Inst. of Tech.,Madras, India
Feipei Lai, National Taiwan Univ., Taiwan
Xiang Liu, Peking Univ., China
Balakrishnan. M, Indian Inst. of Tech. Delhi, India
Philip Machanick, Univ. of Queensland, Australia
John Morris, Univ. of Auckland, New Zealand
Tadao Nakamur, Tohoku Univ., Japan
Sukumar Nandi, Indian Inst. of Tech.,Guwahati, India
Tin-Fook Ngai, Intel China Research Center, China
Andrew Paplinski, Monash Univ., Australia
Lalit Patnaik, Indian Inst. of Science, India
Jih-Kwon Peir, Univ. of Florida, USA
Damu Radhakrishnan, State Univ. of New York, USA
Rajeev Thakur, Argonne National Laboratory, USA
Tanya Vladimirova, Univ. of Surrey Guildford, UK
Weng-Fai Wong, National Univ. of Singapore, Singapore
Chengyong Wu, Inst. of Computing Tech., CAS, China
Yuanyuan Yang, State Univ. of New York, USA
Pen-Chuang Yew, Univ. of Minnesota, USA
Weimin Zheng, Tsinghua Univ., China
Chip Hong Chang, Nanyang Tech. Univ., Singapore
Vinod Prasad, Nanyang Tech. Univ., Singapore
Douglas Leslie Maskell, Nanyang Tech. Univ., Singapore
Jiajia Chen, Nanyang Tech. Univ., Singapore Xiaoyong Chen, Nanyang Tech. Univ., Singapore
Accepted and presented papers are planned to be published in the Springer-Verlag "Lecture Notes in Computer Science" series (indexed by SCI).
Prospective authors are invited to submit a full paper in *English* (not to exceed 6000 words) presenting original and unpublished research results and experience. Papers will be selected based on their originality, timeliness, significance, relevance, and clarity of presentation. It is understood that papers in new areas are likely to contain less quantitative evaluations and comparisons than those in more established areas.
Submissions will be carried out electronically via
http://www.acsac05.ntu.edu.sg/submit.htm
Papers must be submitted in PDF (preferably) or Postscript that is interpretable by Ghostscript.
Submissions imply the willingness of at least one author to register, attend the conference, and present the paper.
Call For Papers - PACT'05
International Conference on
Parallel Architectures and Compilation Techniques
Saint Louis, Missouri, September 17-21, 2005
http://www.pactconf.org/pact05
The purpose of PACT is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest. PACT solicits novel papers on a broad range of topics that include, but are not limited to:
Information for Authors
Abstract submissions are due March 23rd, 2005 and paper submissions are due
March 30th 2005. No extensions will be granted. Detailed instructions for
electronic submission and other important dates will be posted on the PACT
conference web site (http://www.pactconf.org/pact05). For additional
information
regarding paper submission, please contact the Program Chair, Kathryn McKinley
(mckinley@cs.utexas.edu).
Tutorials / Workshops
Proposals are solicited for tutorials and workshops to be held during the
conference. Interested individuals are invited to submit proposals to the
Workshop
chair, Jose Martinez (martinez@csl.cornell.edu), and the Tutorials chair, Craig
Zilles
(zilles@cs.uiuc.edu).
Organizing Committee
General Chair:
Josep Torrellas, UIUC
Program Chair:
Kathryn McKinley, UT - Austin
Steering Committee:
Gabby Silberman, IBM
Michel Cosnard, INRIA & UNSA
Kemal Ebcioglu, IBM
Ulrich Finger, EURECOM
Jean-Luc Gaudiot, UCI
Mary Hall, ISI/USC
David Kaeli, Northeastern
David Koppelman, Louisiana State
Josep-L. Larriba-Pey, UPC
Vivek Sarkar, IBM
Mateo Valero, UPC
Program Committee:
David Albonesi, Cornell
Steve Carr, MTU
John Carter, Utah
Keith Cooper, Rice
Jack Davidson, UVA
Amer Diwan, CO
Sandhya Dwarkadas, Rochester
Seth Goldstein, CMU
David Grove, IBM
Sam Guyer, UT
Mary Hall, ISI
Daniel Jimenez, Rutgers
Norm Jouppi, HP
Wolfgang Karl, Karlsruhe
Christos Kozyrakis, Stanford
Chandra Krintz, UC - Santa Barbara
Scott Mahlke, Michigan
Margaret Martonosi, Princeton
Samuel Midkiff, Purdue
Trevor Mudge, Michigan
Shubu Mukherjee, Intel
Keshav Pingali, Cornell
Steve Reinhardt, Michigan
Greg Steffan, Toronto
Olivier Temam, Inria
Zhenlin Wang, MTU
Local Arrangements Chair:
Patrick Crowley, Washington U. in St. Louis
Publicity Co-Chairs:
Americas: Milos Prvulovic, Georgia Tech
Europe: Eduard Ayguade, UPC
Asia/Pacific: Greg Egan, Monash University
Workshops Chair:
Jose Martinez, Cornell
Tutorials Chair:
Craig Zilles, UIUC
Publications Chair:
Ras Bodik, UC - Berkeley
Web Chair:
Jose Renau, UC - Santa Cruz
Registration Chair:
Rajiv Gupta, Arizona
Finance Chair:
Wei Liu, UIUC
Industry Liaison Co-Chairs:
Avi Mendelson, Intel
Gabby Silberman, IBM
Call for Papers TACS-2: Second Workshop on Temperature-Aware Computer Systems
Sunday, June 5, 2005 Held in conjunction with ISCA-32, Madison, WI, USA, June 4-8, 2005
Important Dates:
Submission deadline: April 4, 2005
Author notification: May 3, 2005
Final manuscripts: May 20, 2005
Many analysts suggest that increasing power density and resulting difficulties in managing on-chip temperatures are some of the most urgent obstacles to continued scaling of VLSI systems within the next five to ten years. Just as has been done before for power-aware computing, "temperature-aware" computing must be approached not just from the packaging and circuit-design communities, but also from the processor- and systems- architecture communities. Many techniques for managing operating temperature will use power-management techniques, but possibly in different ways than for energy efficiency. There is growing interest in cooling solutions from the processor- and systems-architecture domains, as evidenced by recent work on fetch throttling, dynamic voltage scaling, and process scheduling in response to thermal stress; and some progress has been made on modeling infrastructure for this kind of research. But research so far has only scratched the surface of what is possible. This topic area presents a wide-open field for new research, with lots of "low-hanging fruit", and interesting opportunities for wide-ranging inter-disciplinary work.
This workshop will serve as a forum to explore a broad spectrum of topics pertaining to temperature-aware computer systems, for researchers from multiple fields to exchange ideas and initiate collaborations, and to continue establishing temperature-aware computing as an important research topic in its own right. Conributions from all aspects of temperature-aware design are encouraged, related topics like reliability, leakage, thermal sensors, etc.
We especially encourage submissions involving collaboration between architects and thermal engineers! In fact, the goal of this workshop is to stimulate the widest possible collaboration among architects and other engineers on topics related to temperature-aware design.
This is the second year of the TACS workshop. Last year's TACS, held in conjunction with ISCA-31, was extremely successful, with good attendance, four strong papers covering diverse topics, an exciting keynote speech by Luiz Barroso of Google, and a vigorous panel discussion.
Organizers:
Kevin Skadron, Univ. of Virginia Dept. of Computer Science David Brooks, Harvard Division of Engineering and Applied Sciences
Program Committee:
Kaveh Azar, Q Advanced Thermal Solutions, Inc.
Frank Bellosa, Univ. of Karlsruhe
David Copeland, Sun Microsystems
José González, Intel Barcelona Research Center
Steve Gunther, Intel
Herve Jaouen, ST Microelectronics, Crolles, France
Avi Mendelson, Intel Israel
Li-Shiuan Peh, Princeton Univ.
Jude Rivers, IBM TJ Watson
M. Nabil Sabry, Univ. Française d'Egypte
Mircea Stan, Univ. of Virginia
Please send questions to: skadron |at| cs DOT virginia DOT edu