Welcome to IEEE TCCA Email-Monthly, May 2003:
Madrid, Spain, February 14-18, 2004 Paper Due date: July 14, 2003
Submitted by: Jose F. Martinez <hpca@csl.cornell.edu>
Call For Papers: URL: http://www.ac.uma.es/hpca10/
2. PACT 2003 Workshops: - AGridM; MEDEA; SNAPI; SPDSEC
New Orleans, LA September 27 - October 1, 2003,
Paper Due date: June 16, 2003
Submitted by: Dieter Kranzlmueller, <pact2003@gup.jku.at>
Website: http://www.ccs.neu.edu/pact03/ -> Workshops
3. ISCA-2003: International Symposium on Computer Architecture
San Diego, California, USA, June 9-11, 2003
Submitted by: Yuanyuan Zhou <yyzhou@cs.uiuc.edu>
Call for Participation: http://www.regmaster.com/fcrc2003.html
4. The 15th Symposium on Computer Architecture and High Performance Computing
Sao Paulo/SP - Brazil - November 10-12, 2003
Paper Due date: June 23, 2003
Submitted by: Jean-Luc Gaudiot <gaudiot@uci.edu>
Call For Papers: http://www.pcs.usp.br/~sbac2003/
5. Computer Architecture Letters
Submitted by: Kevin Skadron <skadron@cs.virginia.edu>
Website: <http://www.comp-arch-letters.org>
send an email to
qyang@ele.uri.edu
<http://www.computer.org/TCsignup/index.htm>
Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Call for Papers
HPCA-10
10th International Symposium on High-Performance Computer Architecture
Madrid, Spain
February 14-18, 2004
http://www.ac.uma.es/hpca10/
The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit full papers on all aspects of high-performance computer architecture.
Topics of interest include, but are not limited to:
+ Processor architectures
+ Cache and memory architectures
+ Parallel computer architectures
+ Impact of VLSI scaling techniques
+ Novel architectures for emerging applications
+ Power-efficient architectures
+ High-availability architectures
+ High-performance I/O architectures
+ Embedded and reconfigurable architectures
+ Real-time architectures
+ Interconnect and network interface architectures
+ Network processor architectures
+ Innovative hardware/software trade-offs
+ Simulation and performance evaluation
+ Benchmarking and measurements
Please check the conference web site for submission information:
http://www.ac.uma.es/hpca10/
The submission should not exceed twelve pages in IEEE double column format. Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. The official submission deadline is July 14, 2003 at 9pm Pacific Time USA. An automatic extension of one week will be given without request. No further extensions will be given. Papers may be submitted for blind review at the option of the authors. Please indicate whether the paper is a student paper for best student paper nominations. Please submit proposals for workshops to the workshops chair by July 14, 2003.
Important dates:
Paper submission deadline: July 14, 2003
Workshop proposals due: July 14, 2003
Author notification: Oct. 6, 2003
Camera ready copy due: Nov. 3, 2003
Call for Papers: PACT 2003 Workshops:
- AGridM 2003: Adaptive Grid Middleware
- MEDEA 2003: Memory Access Decoupled Architectures and Related Issues
- SNAPI 2003: Storage Network Architecture and Parallel I/Os
- SPDSEC 2003: Hardware/Software Support for Parallel and Distributed
Scientific and Engineering Computing
Submission Deadline: June 16, 2003
PACT 2003 Workshops
The following workshops will be held together with PACT:
and Related Issues
Parallel I/Os
and Distributed Scientific and Engineering Computing
All workshops follow the following schedules:
Submission Deadline: June 16, 2003 Author Notification: July 14, 2003 Final Papers Due: September 1, 2003
For submission procedures and special announcements, please check the individual workshop webpages for specific information.
For general questions about workshops at PACT or to propose additional workshops, please contact the workshop chair Martin Schulz (schulz@csl.cornell.edu).
Please also check:
http://www.ccs.neu.edu/pact03/ -> Workshops
AGridM 2003: Workshop on Adaptive Grid Middleware
Organizers:
Wilson Rivera and Jaime Seguel, University of Puerto Rico Mayaguez, USA
Scope:
Grid computing research focuses on building a large-scale computing
infrastructure by linking computing facilities at many distributed
locations. By analogy with the electric power Grids, such systems
are known as computational Grids. Significant effort has been spent
in the design and implementation of middleware software for enabling
computational Grids. These software packages have been successfully
deployed and it is now possible to build clusters beyond the boundaries
of a single local area network. However, the challenging problem of
dynamically allocating resources in response to application requests
for computational services remains unsolved. Adaptive middleware is
software that resides between the application and the computer operating
system and enables an application to adapt to changing availability of
computing and networking resources.
The purpose of this workshop is to provide an open forum for researchers from hardware and software areas to present, discuss, and exchange research-related ideas, results, and experiences in the area of adaptive middleware for computational Grids.
Workshop webpage:
http://ece.uprm.edu/agridm2003
MEDEA 2003: Workshop on Memory Access Decoupled Architectures and Related Issues
Organizers:
Sandro Bartolini, University of Siena, Italy
Pierfrancesco Foglia and Cosimo Antonio Prete, University of Pisa, Italy
Scope:
MEDEA-2003 aims to continue the high level of interest in the first three
MEDEA Workshops held with PACT'00, PACT'01 and PACT'02.
Due to the ever-increasing gap between CPU and memory speed, there is a great interest in evaluating and proposing processor, multiprocessor and system architectures dealing with the "memory wall" problem. In this scenario, memory performance issues can be better addressed when considering system architecture and application domain in a joint manner. In fact, it is the combined effect of the applications and the system on which they are executing that stresses the memory subsystem and pushes towards specific solutions. Typical architectural choices include single processor vs. multiprocessor solutions, single chip vs. COTS design, superscalar, multithreaded or VLIW architectures. Application domains encompass commercial (Web, DB, e-business, and multimedia), embedded (personal, mobile, automotive, automation and medical), networking applications, etc.
The MEDEA-2003 Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience on the design and evaluation of architectures for embedded, commercial and general purpose systems. Main topics are memory performance issues and olutions in the various application domains.
Workshop webpage:
http://garga.iet.unipi.it/medea03/
SNAPI 2003: Workshop on Storage Network Architecture and Parallel I/Os
Organizer:
Qing (Ken) Yang, University of Rhode Island, USA
Scope:
Data are the "life-blood" of computing and the main asset of any
organization.
Therefore, disk I/O and data storage on which data reside are becoming
"first
class citizens" in today's information world. This workshop intends to bring
together researchers and practitioners from academia and industry to discuss
cutting edge research on parallel and distributed data storage technologies.
By discussing ongoing research, the workshop will expose participants to the
most recent developments in storage network architectures and parallel I/O.
Workshop webpage:
http://www.ele.uri.edu/tcca/SNAPI_CFP.html
SPDSEC 2003: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing
Organizers:
Minyi Guo, University of Aizu, Japan
Laurence Tianruo Yang, Francis Xavier University, Canada
Scope:
The field of parallel and distributed processing has obtained prominence
through advances in electronic and integrated technologies beginning in
the 1940s. Current times are very exciting and the years to come will
witness a proliferation in the use of parallel and distributed systems,
or supercomputers. The scientific and engineering application domains
have a key role in shaping future research and development activities
in academia and industry.
The purpose of this workshop is to provide an open forum for computer scientists, computational scientists and engineers, applied mathematicians, and researchers to present, discuss, and exchange research-related ideas, results, works-in-progress, and experiences in the areas of architectural, compilation, and language support for problems in science and engineering applications.
Workshop webpage:
http://juliet.stfx.ca/people/fac/lyang/pact03-spdsec/
ISCA-2003 Call for Participation
The 30th Annual International Symposium on Computer Architecture
San Diego, California, USA June 9-11, 2003
http://isca03.cs.princeton.edu/
http://www.regmaster.com/fcrc2003.html
On behalf of the general chair, Allan Gottlieb, the program chair, Kai Li, and the ISCA-2003 organizing committee, we encourage you to attend the 30th Annual International Symposium on Computer Architecture in beautiful San Diego, CA. ISCA is the premier technical forum on computer architecture and this year is a great opportunity to interact with colleagues in the conjunct 2003 Federated Computer Research Conference (FCRC) event. We encourage you to participate and attend the conference.
The final program is available at
http://isca03.cs.princeton.edu/program.htm
The travel grants application for students is available at
http://isca03.cs.princeton.edu/grants.htm The application deadline is May 9th, 2003.
The workshop and tutorial information is available at http://isca03.cs.princeton.edu/workshops.htm
SBAC-PAD 2003
Call for Papers
The 15th Symposium on Computer Architecture and High Performance Computing
Sao Paulo, November 10-12 2003
http://www.pcs.usp.br/~sbac2003
SBAC-PAD is an international annual conference, started in 1987, which has continuously presented an overview of new developments, applications, and trends in parallel and distributed computing technologies. SBAC-PAD is open for faculty members, researchers, specialists and graduate students around the world. In this edition, the symposium will be held in S?o Paulo. In Brazil, Sao Paulo is one of the most important cities in the economical,cultural and technological areas. Authors are invited to submit manuscripts on all aspects of computer architecture and high performance computing. Topics of interest include (but are not limited to):
To submit an original research, please register your manuscript, in English, not exceeding 8 pages (double column). Submissions must be in PDF or Postscript format. Please check the following web site for paper submission information:
http://www.pcs.usp.br/~sbac2003
Submissions will be reviewed internationally. Accepted papers are expected to be submitted camera-ready in full length and to be presented at the conference. Simultaneous submission to other conferences with published proceedings is strongly discouraged.
Important Deadlines
Paper submission deadline June 23, 2003
Tutorial Proposals June 23, 2003
Author Notification July 28, 2003
Camera Ready Copy August 11, 2003
Conference November 10-12, 2003
General Chair
L?ria M. Sato
Universidade de S?o Paulo (USP)
Program Chair
Philippe O. A. Navaux
Universidade Federal do Rio Grande do Sul (UFRGS)
Program Committee
Adriano J. O. Cruz (Brazil)
Alba C. M. A. Melo (Brazil)
Alberto F. De Souza (Brazil)
?lvaro L. G. A. Coutinho (Brazil)
Bertil Folliot (France)
Brigitte Plateau (France)
Celso L. Mendes (USA)
C?sar A. F. De Rose (Brazil)
Claude Girault (France)
Claudio F. R. Geyer (Brazil)
Claudio L. Amorim (Brazil)
David A. Padua (USA)
Denis Trystram (France)
Edil S. T. Fernandes (Brazil)
Eduardo W. Bergamini (Brazil)
Felipe M. G. Fran?a (Brazil)
Guang R. Gao (USA)
Hans-Ulrich Heiss (Germany)
Horst D. Simon (USA)
Jack Dongarra (USA)
Jairo Panetta (Brazil)
Jean-Luc Gaudiot (USA)
Jos? H. Saito (Brazil)
Jos? N. Amaral (Canada)
L?ria M. Sato (Brazil)
Liviu Iftode (USA)
Luiz A. Barroso (USA)
Luiz De Rose (USA)
Mario Nemirovsky (USA)
Mark Crovella (USA)
Mateo Valero (Spain)
Nader Bagherzadeh (USA)
Orlando G. Loques (Brazil)
Peter Allan (UK)
Philippe O. A. Navaux (Brazil)
Rafael D. Lins (Brazil)
Renato S. Silva (Brazil)
Ricardo Bianchini (USA)
Ron Perrott (North Ireland)
Ronaldo A. L. Gon?alves (Brazil)
S?rgio T. Kofuji (Brazil)
Siang W. Song (Brazil)
Tadao Nakamura (Japan)
Tiaraju A. Diverio (Brazil)
Valmir C. Barbosa (Brazil)
Wagner Meira Jr (Brazil)
Walfredo C. Cirne (Brazil)
Organizing Committee
Edson T. Midorikawa (PCS/EPUSP/USP)
Jo?o A. Zuffo (LSI/EPUSP/USP)
Edson dos S. Moreira (CCE/USP)
Mar?lia J. Caldas (LCCA/USP)
Luis C. Trevelin (UFSCAR)
Edmundo Castro (CENAPAD-SP)
Maur?cio L. Pilla (UFRGS)
Leonardo A. de P. e Silva (UFRGS)
Computer Architecture Letters is pleased to announce the publication of another paper online at our website, <http://www.comp-arch-letters.org>; the abstract appears below. The papers will appear in print in our next paper issue. The print issues are distributed to the entire IEEE Computer Society TCCA membership, and e-mail notifications of newly accepted papers are sent on a regular basis to the TCCA and ACM SIGARCH memberships.
The objective of Letters is to publish short (4-page), timely articles of high-quality work. We are very much aware of the long delays in our field between submissions of manuscripts and their eventual appearance in print. We are doing something about that with this journal. After a little more than one year of operation, we have maintained an average turnaround time from submission to author notification of just one month, with an acceptance rate of 20%.
We encourage the community to continue submitting papers to Letters. Submissions are welcomed on any topic in computer architecture, especially but not limited to:
Abstract:
This paper proposes a single-ISA heterogeneous multi-core architecture as a mechanism to reduce processor power dissipation. It assumes a single chip containing a diverse set of cores that target different performance levels and consume different levels of power. During an application's execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements. It describes an example architecture with five cores of varying performance and complexity. Initial results demonstrate a five-fold reduction in energy at a cost of only 25% performance.