Welcome to IEEE TCCA Email-Monthly, July 2004:
*Available at http://www.hotchips.org *Early Registration Deadline: Aug. 1, 2004 *Submitted by: Alan Smith <smith@EECS.Berkeley.EDU>
*Washington, D.C. September 8-10, 2004 *Website: http://www.klabs.org/mapld04/reg/registration.html *Early Registration Closes August 9, 2004
*In conjunction with PACT04 *September 29 - October 3, 2004, Antibes Juan-les-pins, French *Call for Papers: http://rcf.unl.edu/~abacus/SNAPI_04/ *Submission deadline: Extended to: July 16th, 2004 -Submitted by: Hong Jiang <jiang@cse.unl.edu>
send an email to
qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at <http://www.computer.org/TCsignup/index.htm>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ HotChips 16 Advance Program
and Registration Information
Sunday, August 22, 2004
8:30-12:00 Morning Tutorial
Ultrawideband; Technology and Issues
Roberto Aiello Staccato Communications
Anuj Batra Texas Instruments
Sandeep Kumar Adimos
plus others To Be Announced
This tutorial delves into the major issues surrounding the emerging UWB environment. We discuss some of the fundamental technology issues of this PHY in both the analog and digital domains. This topic is elaborated using real world designs to consider the key system level issues that manifest in UWB based designs. We follow the technology discussions with target market descriptions and explore the opportunities that UWB technologies enable. Our discussions are hosted by the drivers behind UWB, system architects and chip implementers. They describe and discuss the tradeoffs that they faced during their development of the UWB specs and the initial implementations.
12:00- 1:30 lunch
1:30- 5:00 Afternoon Tutorial
Performance Comparison of State-of-the-Art Volatile and Non-Volatile
Memory Devices
J. Thomas Pawlowski Micron Technology
Between vendor vested interests, presentation hype and datasheet specsmanship, it is often difficult to determine which memory devices are truly the most appropriate for an application in question. This is true for both volatile (DRAM, SRAM and pseudo-SRAM) and non-volatile (NOR and NAND FLASH) memory devices. This 3 hour tutorial will objectively examine the memories available today and in the reasonably near future, including SRAMs such as QDR II, DDR II and QDR III; DRAMs such as DDR2, GDDR3, FCRAM, RLDRAM and XDR, low-power volatile memory devices such as LPDRAM and PSRAM, and low-power non-volatile memory devices such as NOR and NAND FLASH. A brief description will be made concerning external operation of the major devices and where necessary some description of internal operation. The devices will be compared by performance (usable bandwidth under various operating scenarios, energy usage under these scenarios and signal count). Example operating scenarios include random operations, streaming requests with defined read/write ratios and resource predictability, streaming requests with defined read/write ratios but no predictable resource availability, etc. Performance comparisons are made using a cycle-accurate memory comparison software tool written by the author and empirically verified. Cost factors will be considered, including silicon area and test cost of competing architectures. A brief attempt will be made to assess market size and dynamics of the major devices where possible. Conclusions will be drawn for each major operating scenario concerning performance/cost ratios. Wherever possible, practical application examples will be illustrated to make the operating scenarios relevant to the system design tasks faced today and in the reasonably near future.
As Senior Director of Architecture Development in Micron's NetCom Group, J. Thomas Pawlowski is responsible for Micron memory product definition for networking and communications applications including products built on DRAM and FLASH processes. During his tenure at Micron, Thomas has created or co-created the following DRAM and SRAM devices: reduced latency DRAM II (RLDRAM II); pipelined, burst, synchronous SRAM (used in Pentiumï¿&fraq12; and PowerPCï¿&fraq12; systems); Zero Bus Turnaround. (ZBTï¿&fraq12;) SRAM (used in network and communication systems); Double Data Rate (DDR) SRAM; and Quad Data Rate (QDR) SRAM (versions I, II, and III). Thomas holds over 70 U.S. and international patents with more pending.
Monday, August 23, 2004
8:30- 8:40 Welcome, Opening Remarks
General Chair: Robert Lashley
Program Co-Chairs: Bill Dally, Keith Diefendorff
8:40-10:10 Session 1: Mobile Processing
Bulverde - An Applications Processor for Phone and PDA Applications
Nigel Paver - Intel SC10: A Video Processor and Pixel Shading GPU For Handheld Devices
Edward Hutchins - NVIDIA SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power
SoC Design Platform Hiroyuki Mizuno - Hitachi
10:10-10:30 Break
10:30-11:30 Keynote: Robert Denise (JPL)
Mars Exploration Rovers -- a View from the Inside
11:30-12:30 Session 2: High-End Audio and Video
Quartet: A Pipeline-Interleaved Multithreaded Audio DSP
Carl Wakeland, Tom Savell - Creative Labs CS7050 High Performance H.264/AVC Hardware Video Decoder Core for
Multimedia SOC's Jill Cush - Amphion Semiconductor
12:30- 1:30 Lunch
1:30- 2:30 Session 3: Wireless Communication
IEEE802.11a Based Wireless AV Module with Digital AV Interface
Takashi Wakutsu - Toshiba Single Chip CMOS Direct Conversion Transceivers for WWAN and WLAN
Tajinder Manku - Sirific Wireless
2:30- 2:50 Break
2:50- 4:20 Session 4: Media and Graphics Processing
The GeForce 6800 GPU John Montrym, Henry Moreton - NVIDIA New Media Architecture for Next Generation Application Processors
Gerard Williams - ARM
The MXP5800 Media Processor Lou Lippincott - Intel
4:20- 4:50 Break
4:50- 6:20 Session 5: Enabling Technology
Simnow: An Extremely Fast and Accurate Platform and Processor Simulator
Robert Bedichek - AMD
Microchannel Liquid Cooling Solutions
Mark Munch, Jim Hom, Girish Upadhya, Peng Zhou- Cooligy
A New System-On-Chip Bus Architecture Optimized for 1GHz MIPS Processors
John Kinsel, Anna Chiang - PMC-Sierra
6:20- 7:30 Dinner
7:30- 9:30 Panel: Outsourcing Engineering Development Offshore
Moderator: John Nickolls NVIDIA
Panelists: Vinod Dham NewPath Ventures
Ron Hira IEEE-USA, Rochester Inst. Technology
Carl Everett Accel Partners
plus others To Be Announced
Tuesday, August 24, 2004
8:40-10:10 Session 6: Potpourri
MDGRAPE-3 chip: A 165-Gflops application-specific LSI for molecular
dynamics simulations Makoto Taiji - RIKEN Accelerating Next-Generation Public-key Cryptography on General-Purpose
CPUs Hans Eberle - Sun How SolarFlare Communications broke the 10Gbps on UTP barrier
Ron Cates - SolarFlare
10:10-10:30 Break
10:30-11:30 Keynote: Steve Jurvetson (Draper Fisher Jurvetson)
Nanotech and the Future of Moore's Law
11:30-12:30 Session 7: Embedded Systems
A Fast Powertrain Microcontroller Erik Norden - Infineon The Mote Revolution: Low Power Wireless Sensor Network Devices
Joseph Polastre - UC Berkeley
12:30- 1:30 Lunch
1:30- 2:30 Session 8: Low-Power Processors
A 90nm embedded DRAM single chip LSI with a 3D graphics, H.264 codec
engine, and a reconfigurable processor Masanobu Okabe - Sony
A Low-Power Opteron Processor Mike Leary - AMD
2:30- 2:50 Break
2:50- 4:20 Session 9: Instruction Set Automation
The End of ISA Design: Power Tools for Optimal Processor Generation
David Goodwin - Tensilica Long Words and Wide Ports: Reinventing the Configurable Processor
Dhanendra Jani, Gulbin Ezer, James Kim - Tensilica
OptimoDEJ Krisztian Flautner - ARM
4:20- 4:50 Break
4:50- 6:20 Session 10: High-End Processors
The Montecito Processor Cameron McNairy, Rohit Bhatia - Intel A 32-way Multithreaded SPARC Processor Poonacha Kongetira - Sun Intel Pentium 4 Processor on 90nm Technology Ronak Singhal - Intel
6:20- 6:30 Closing Remarks
Registration for HOT Chips 16 is available through our secure web server at http://www.hotchips.org
Payment can be made with all common credit cards. A receipt can be printed after the registration is completed and a confirmation email will be sent to the email address provided. Discounted early registration rates apply if payment is completed on or before August 1, 2004. Online registration will continue to be available until August 20, 2004 at the higher Late/Onsite registration rate. After August 20, 2004 all registrations must be done
on-site at the conference.
Refund requests must reach us on or before August 1, and are subject to a $25 processing fee. Students are required to show valid picture ID cards. Please remember to bring your IEEE or ACM membership number if you are registering on-site.
For answers to questions about registration, contact us by email at:
registration@hotchips.org
For other information, contact us by email at:
info@hotchips.org
Registration Fees
Advance (on/before 8/1) Late (after 8/1)
Tutorials Conf. Both Tutorials Conf. Both
only only only only
Member $75 $240 $315 $150 $380 $530
Non-Member $90 $325 $415 $150 $475 $620
Student $75 $ 95 $170 $ 90 $120 $210
Conference registration includes:
+ Conference Attendance
+ One copy of presentation notes
+ Monday and Tuesday luncheons
+ Coffee breaks
+ Sunday afternoon wine and cheese reception
+ Monday HOT Chips evening dinner and Panel
+ Monday and Tuesday Parking
Tutorial registration includes:
+ Attendance for both Morning and Afternoon tutorials
+ One copy of tutorial notes
+ Sunday Luncheon
+ Coffee breaks
+ Sunday afternoon wine and cheese reception
+ Sunday Parking
Location:
HOT Chips and HOT Interconnects will be held in Memorial Auditorium on the Stanford University campus, Palo Alto, California, approximately 24 miles from San Francisco airport and 15 miles from San Jose airport.
Directions, Maps:
From San Francisco: take Highway 101 south. From San Jose: take Highway 101 north. + Exit 101 at Embarcadero Rd. (west) and drive 3 miles until you
enter Stanford campus on Galvez St. + Keep to the left on Galvez, then turn right at Campus Drive.
Parking is between Galvez and Palm Dr. + Walk along Galvez to the end, then turn right for Memorial
Auditorium, opposite Hoover Tower.
More details can be found on the attendee page on our website at
http://www.hotchips.org/hc16/attendee
Mass transit information is available at
http://www.transitinfo.org/
Maps of Stanford campus and surroundings are at
http://www.stanford.edu/home/visitors/maps.html
Weather:
Mid-August is typically in the 80s (F)/ 30s (C) and sunny during the day.
Nights are much cooler; a light jacket or sweater is appropriate.
Housing:
HOT Chips does not recommend any specific hotel, but refers attendees to the
following Stanford University webpage for related information:
http://www.stanford.edu/dept/hds/scs/individuals/hotelmotel.html
Reservations well in advance are advised.
On campus housing is available in student residences and can be arranged by contacting the Stanford Summer Conference Office at
(650) 725-1429 or
summerhousing@conferences.stanford.edu or http://www.stanford.edu/dept/hds/scs/individuals
MAPLD 2004: Early Registration Open and Program Released
Registration Open
and
Program Announced
7th Mil/Aerospace Applications of Programmable
Logic Devices (MAPLD) International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 8-10, 2004
Hosted by the NASA Office of Logic Design
Registration is now open for the 7th annual MAPLD International Conference, September 8-10, 2004, Washington, D.C.
http://www.klabs.org/mapld04/reg/registration.html
Early Registration Closes August 9, 2004.
The MAPLD program features approximately 130 technical presentations in a variety of sessions, seminars, and workshops, as well as over 30
Industrial and Government Exhibits covering programmable logic devices and technologies, digital engineering, and related fields for military and aerospace applications. Devices, technologies, logic design, flight applications, fault tolerance, usage, reliability, radiation susceptibility, and encryption applications of programmable devices, processors, and adaptive computing systems in military and aerospace systems are among the subjects for the conference. Abstracts are available on-line, via the conference home page.
The Invited Speaker program will include:
WELCOME AND OPENING REMARKS
Jim Nehman, Director of Development Programs
NASA Office of Exploration Systems
-and-
INVITED HISTORY TALK
Captain John W. Young
NASA Johnson Space Center
SEMINARS - Two full-day seminars will be presented:
^ï¿&fraq12; VHDL Synthesis for High-Reliability Systems
^ï¿&fraq12; Aerospace Mishaps and Lessons Learned
PANEL SESSION:
^ï¿&fraq12; "Why Is Space Exploration So Hard? The Roles of Man and Machine"
WORKSHOPS & "BIRDS OF A FEATHER" SPECIAL SESSIONS
^ï¿&fraq12; Mitigation Methods for Reprogrammable Logic in
The Space Radiation Environment
^ï¿&fraq12; Reconfigurable Computing - New Extended Format!
^ï¿&fraq12; PLD Failures, Analyses, and the Impact on Systems - NEW for 2004!!!
^ï¿&fraq12; Digital Engineering and Computer Design - A Retrospective and
Lessons Learned for Today's Engineers
* Includes a disassembly and discussion of a Block II
Apollo Guidance Computer by the engineers who designed it.
^ï¿&fraq12; "An Application Engineer's View" - Back for 2004!
^ï¿&fraq12; "NESC and Software" - a joint session of MAPLD and the NASA
Engineering and Safety Center
TECHNICAL SESSIONS:
^ï¿&fraq12; Applications: Military and Aerospace
^ï¿&fraq12; Systems and Design Tools
^ï¿&fraq12; Radiation and Mitigation Techniques
^ï¿&fraq12; Logic Design and Processors
^ï¿&fraq12; Reconfigurable Computing, Evolvable Hardware, and Security
^ï¿&fraq12; Poster Session
INDUSTRIAL and GOVERNMENT EXHIBITS RESERVATIONS:
NASA Office of Logic Design Mentor Graphics Corporation
Xilinx Corporation Synthworks
Tensilica Actel Corporation
Annapolis Microsystems Space Micro, Inc.
SEAKR Engineering Aldec
IEEE Aerospace and Electronics Systems Society
Hier Design Global Velocity
Lattice Semiconductor Quicksilver Technology
Celoxica BAE Systems
The Andraka Consulting Group Aeroflex
Synopsys Peregrine Semiconductor
Starbridgesystems Condor Engineering
AccelChip NASA Engineering and Safety Center
Synplicity Defense Microelectronics Activity
Southwest Research Institute Altera
SRC Computers Mathstar
Sigrity US Semiconductor Corp.
ProDesign Mission Research Corporation
CONFERENCE HOME PAGE - http://klabs.org/mapld04 - contains
an abundance of information on both technical and programmatic aspects of the conference. This conference is open to US and foreign participation and is not classified. For related information, please see the NASA Office of Logic Design Web Site (http://klabs.org).
International Workshop on Storage Network Architecture and Parallel I/Os
To be held with the 13th International Conference on Parallel Architectures and Compilation Techniques,
September 29 - October 3, 2004, Antibes Juan-les-pins, French Data are the "life-blood" of computing and the main asset of any organization. Therefore, disk I/O and data storage on which data reside are becoming "first class citizens" in today's information world. This workshop intends to bring together researchers and practitioners from academia and industry to discuss cutting edge research on parallel and distributed data storage technologies. By discussing ongoing research, the workshop will expose participants to the most recent developments in storage network architectures and parallel I/O. Topics of interest include but are not limited to:
Authors are invited to submit an extended abstract no longer than 4 pages for
consideration. Submissions should be viewable by Adobe Acrobat Reader
(version 3.0 or higher). Accepted papers must be no longer than 8 single-spaced
pages (including figures, references, and appendices) using 12pt font.
Submit an electronic copy of the abstract in PDF format online
at (http://rcf.unl.edu/abacus/SNAPI_04) or by email to jiang@cse.unl.edu by
June 23rd.
Notification of acceptance will be sent out by July 14th, and camera-ready
papers will be due by September 1st. All accepted papers will be presented at
the workshop, will be included in a workshop proceedings booklet (distributed
at the workshop), and will be made available online.
Important dates:
Paper submission: July 16th
Notification of acceptance: July 24th
Final Camera-ready paper: September 1st
Organizer:
Hong Jiang
Dept. of CSE
University of Nebraska - Lincoln
Lincoln, NE 68588-0115 USA
Phone: 402-472-6747
Fax: 402-472-7767
E-mail: jiang@cse.unl.edu
Co-Organizer
Qing (Ken) Yang
Dept. of ECE
University of Rhode Island
Kingston, RI 02881
Email: qyang@ele.uri.edu
Tel: 401-874-5880
Fax: 401-782-6422
Program Committee:
Ahmed Amer, University of Pittsburgh, USA
Roger Chamberlain, Washington University, St. Louis, USA
Xubin (Ben) He, Tennessee Technological University, USA
Yiming Hu, University of Cincinnati, USA
David R. Kaeli, Northeastern University, USA
Dhabaleswar K. Panda, Ohio State University, USA
Jehan-Francois Paris, University of Houston, USA
Xiao Qin, New Mexico Tech, USA
Dilma Da Silva, IBM T.J. Watson Research Center, USA
Peter Sobe, University of Lubeck, Germany
Fujita Tomonori, NTT Network Innovation Laboratories, Japan
Jun Wang, University of Nebraska - Lincoln, USA