Welcome to IEEE TCCA Email-Monthly, July 2005.
*September 18, 2005, St. Louis, MO, Held in conjunction with PACT-14 *Abstracts due: 08/01/2005 *Submitted by: David Kaeli <kaeli@ECE.NEU.EDU> *Call for Papers: www.ece.neu.edu/conf/WBIA/
*February 11-15, 2006, Austin, Texas, *Abstracts due: July 11, 2005, Full Paper Due:July 18, 2005 *Submitted by: Ki Hwan Yum <yum@cs.utsa.edu> *Call for Papers: http://www.hpcaconf.org/hpca12
Architecture Research *http://www.cra.org/Activities/grand.challenges/architecture/home.html *Submitted by Mary Jane Irwin, mji@cse.psu.edu
*http://www.cse.psu.edu/~mdl/jetc/ *Submitted by Vijay Narayanan, vijay@cse.psu.edu
Letters *Submitted by: Kevin Skadron <skadron@cs.virginia.edu> *Website: <http://www.comp-arch-letters.org>
*Saint Louis, Missouri, September 18, 2005 *SUBMISSION DEADLINE: July 10, 2005 *Call for Papers: http://rcf.unl.edu/~abacus/SNAPI_05/
send an email to
qyang@ele.uri.edu
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Workshop on Binary Instrumentation and Applications
Held in conjunction with the 14th International Conference on
Parallel Architectures and Compilation Techniques
PACT-14
St. Louis, MO
September 18, 2005
Topics:
This workshop provides a forum for researchers to present
their work on binary instrumentation systems and applications.
Binary instrumentation has been shown to be an effective technique to
support program analysis, debugging, security, and simulation. A
number of binary instrumentation tools and runtime systems
have been developed. Binary instrumentation can be effectively
implemented statically (at compile or link time) or dynamically
(at run time). This workshop will provide researchers with an
opportunity to exchange ideas and learn about new tools and applications.
This workshop will consider papers that address range of topics, including:
Authors should submit a 2-page abstract to the workshop organizers by 8/1/2005. All submissions should be in PDF format. Authors of accepted papers will be asked to provide a camera-ready full paper (8-pages, single-spaced, double-column format) by 9/9/2005. The proceedings of the workshop will be published in ACM SIGARCH News (pending approval).
Important dates:
Program Committee:
For further information about this workshop, contact the workshop organizers at robert.s.cohn@intel.com or kaeli@ece.neu.edu, or go to the workshop URL: www.ece.neu.edu/conf/WBIA/.
Austin, Texas, February 11-15, 2006
http://www.hpcaconf.org/hpca12
The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to:
* Processor architectures * Cache and memory systems * Parallel computer architectures * Impact of technology on architecture * Power-efficient architectures and techniques * High-availability architectures * High-performance I/O systems * Embedded and reconfigurable architectures * Interconnect and network interface architectures * Network processor architectures * Innovative hardware/software trade-offs * Impact of compilers on architecture * Performance evaluation of real machines
Authors should submit an abstract before Monday, July 11, 2005, 9pm
PST. They should submit the full version of the paper before Monday,
July 18, 2005, 9pm PST. No extensions will be granted. The full version
should be a PDF file that does not exceed 6,000 words according to the
instructions in http://www.hpcaconf.org/hpca12 Papers that exceed the
length limit or that cannot be viewed using Adobe Acrobat Reader (version
3.0 or higher) may not be reviewed. Papers should be submitted for blind
review. Please indicate whether the paper is a student paper for best student
paper nominations.
Papers will be evaluated based on their novelty, fundamental insights, and
potential for long-term contribution. New-idea papers are encouraged.
Submission issues should be directed to the program chair at
das@cse.psu.edu. Workshop and tutorial submissions should be directed to
the workshop and tutorial chair.
Important dates
* Abstract submission deadline : July 11, 2005, 9pm PST (firm deadline) * Paper submission deadline: July 18, 2005, 9pm PST (firm deadline) * Workshop and tutorial proposals due: August 12, 2005 * Author notification: October 7, 2005
Sponsored by the IEEE Computer Society TC on Computer Architecture
General Co-Chairs:
Yale Patt, UT Austin
Craig Chase, UT Austin
Program Chair:
Chita R. Das, Penn State
Program Committee:
Laxmi Bhuyan, UC Riverside
Ricardo Bianchini, Rutgers Univ.
David Brooks, Harvard
Doug Burger, UT Austin
Derek Chiou, UT Austin
Frederic T. Chong, UC Davis
Dan Connors, Colorado
Tom Conte, NCSU
Srini Devadas, MIT
Jose Duato, Univ. Politecnica Valencia
Michel Dubois, USC
Rajiv Gupta, Arizona
James C. Hoe, CMU
Ravi Iyer, Intel
Mahmut Kandemir, Penn State
Eun Jung Kim, Texas A&M
Mikko Lipasti, Univ. of Wisconsin
Kai Li, Princeton
Scott Mahlke, Michigan
Randy Moulic, IBM T.J. Watson
Trevor Mudge, Michigan
Ashwini Nanda, IBM T.J. Watson
Vijaykrishnan Narayanan, Penn State
Mark Oskin, Washington
Dhabaleswar K. (DK) Panda, OSU
Sanjay Patel, UIUC
Li-Shiuan Peh, Princeton
Milos Prvulovic, GATECH
Michael Shebanow, NVIDIA
Anand Sivasubramaniam, Penn State
Per Stenstrom, Chalmers University of Technology
Josep Torrellas, UIUC
Dean M. Tullsen, UCSD
Mateo Valero, Univ. Politecnica Catalunya
Pen-Chung Yew, Minnesota
Qing Yang, Rhode Island
Raj Yavatkar, Intel
Mazin Yousif, Intel
Yuanyuan Zhou, UIUC
Industry Liaison Chair:
Mazin Yousif, Intel
Local Arrangements Chair:
Derek Chiou, UT Austin
Workshop and Tutorial Chair:
Yan Solihin
Publicity and Publications Chair:
Ki Hwan Yum, UT San Antonio
Finance and Registration Chair:
Craig Chase, UT Austin
Web Chair:
Vijaykrishnan Narayanan, Penn State
Steering Committee:
Dharma Agrawal, Univ. of Cincinnati
Laxmi Bhuyan, Univ. of California, Riverside
Jean-Luc Gaudiot, Univ. of California, Irvine
Yale Patt, UT Austin
Josep Torrellas, UIUC
Justin Rattner, Intel
Yuanyuan Zhou, UIUC
Industry Liaison Chair:
Mazin Yousif, Intel
Local Arrangements Chair:
Derek Chiou, UT Austin
Workshop and Tutorial Chair:
Yan Solihin
Publicity and Publications Chair:
Ki Hwan Yum, UT San Antonio
Finance and Registration Chair:
Craig Chase, UT Austin
Web Chair:
Vijaykrishnan Narayanan, Penn State
Steering Committee:
Dharma Agrawal, Univ. of Cincinnati
Laxmi Bhuyan, Univ. of California, Riverside
Jean-Luc Gaudiot, Univ. of California, Irvine
Yale Patt, UT Austin
Josep Torrellas, UIUC
Justin Rattner, Intel
We are delighted to announce that Computer Architecture Letters has been approved as an official publication of the IEEE. Beginning Jan. 2006, newly accepted papers will be posted immediately online in the IEEE Digital Library, in addition to appearing in the next paper issue. Previously published Letters will be also added to the Digital Library in early 2006.
Computer Architecture Letters also announces our two most recent papers, which are publicly available at out website, <http://www.comp-arch-letters.org>. We continue to seek new submissions and remain committed to fast yet accurate review. Our mean time to decision remains one month, with an acceptance rate of approximately 21%.
It is observed that the limited memory space of directmapped caches is not used in balance therefore incurs extra conflict misses. We propose a novel cache organization of a balanced cache, which balances accesses to cache sets at the granularity of cache subarrays. The key technique of the balanced cache is a programmable subarray decoder through which the mapping of memory reference addresses to cache subarrays can be optimized hence conflict misses of direct-mapped caches can be resolved.
The experimental results show that the miss rate of balanced cache is lower than that of the same sized two-way set-associative caches on average and can be as low as that of the same sized four-way set-associative caches for particular applications. Compared with previous techniques, the balanced cache requires only one cycle to access all cache hits and has the same access time as direct-mapped caches.
Chip multiprocessors are of increasing importance due to recent difficulties in achieving higher clock frequencies in uniprocessors, but their success depends on finding useful work for the processor cores. This paper addresses this challenge by presenting a simple compiler approach that extracts nonspeculative thread-level parallelism from sequential codes. We present initial results from this technique targeting a validated dual-core processor model, achieving speedups ranging from 9- 48% with an average of 25% for important benchmark loops over their single-threaded versions. We also identify important next steps found during our pursuit of higher degrees of automatic threading.
International Workshop on Storage Network Architecture and Parallel I/Os
To be held with the 14th International Conference on Parallel Architectures and Compilation Techniques,
Saint Louis, Missouri
Data are the "life-blood" of computing and the main asset of any organization. T herefore, disk I/O and data storage on which data reside are becoming "first cla ss citizens" in today's information world. This workshop intends to bring togeth er researchers and practitioners from academia and industry to discuss cutting e dge research on parallel and distributed data storage technologies. By discussin g ongoing research, the workshop will expose participants to the most recent dev elopments in storage network architectures and parallel I/O. Topics of interest include but are not limited to:
Organizer:
Qing (Ken) Yang
Dept. of ECE
University of Rhode Island
Kingston, RI 02881
Email: qyang@ele.uri.edu
Tel: 401-874-5880
Fax: 401-782-6422
Co-Organizer
Hong Jiang
Dept. of CSE
University of Nebraska - Lincoln
Lincoln, NE 68588-0115 USA
Phone: 402-472-6747
Fax: 402-472-7767
E-mail: jiang@cse.unl.edu