Welcome to IEEE TCCA Email-Monthly, Oct. 2003:
*June 19-23, 2004, Munich, Germany *Paper submission deadline: Nov 7, 2003 -CALL FOR PAPERS: http://isca.in.tum.de/
*February 14-15, 2004, Madrid, Spain. *Workshop URL : http://www.cse.wustl.edu/NP3 *Paper submission deadline: November 3 -submitted by: Patrick Crowley <pcrowley@cse.wustl.edu>
*April 26-27, 2004, Santa Fe, New Mexico *Submission Deadline: Extended to October 20, 2003 -Submitted by: R. Vaidyanathan <vaidy@gigo.ece.lsu.edu> -CALL FOR PAPERS: http://www.ece.lsu.edu/vaidy/raw04/
*Saturday, Feb 14th, 2004, Madrid, Spain *Submission Deadline: Extended to Nov 23rd '03 -Submitted by: Jean-Luc Gaudiot, gaudiot@uci.edu -CALL FOR PAPERS: dragon.kayamba.com/~enric/wepa-1.htm
*October 27, 2003, Eldorado Hotel - Santa Fe, New Mexico -Submitted by: Ben He <hexb@tntech.edu> -Workshop Site: http://cenit.latech.edu/hapcw2003
Biology *April 26, 2004, Eldorado Hotel, Santa Fe, NM *Submission deadline: December 1, 2003 -Submitted by: David A. Bader <dbader@ece.unm.edu> -CALL FOR PAPERS: http://www.cs.ucf.edu/~dcm
*April 26-30, 2004, Santa Fe, New Mexico Eldorado Hotel *Submission Deadline: October 30, 2003 -Submitted by: Nectarios Koziris <nkoziris@cslab.ece.ntua.gr> -CALL FOR PAPERS: http://www.cis.ohio-state.edu/~cac
Architectures
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ISCA-2004 Call for Papers The 31st Annual International Symposium on Computer Architecture
Munich, Germany, June 19-23, 2004
http://isca.in.tum.de/
Papers are solicited for the 31st Annual International Symposium on Computer Architecture. Papers are being sought on all aspects of computer architecture, including (but not limited to) the following:
The DEADLINE for abstract submissions (300 - 600 words) is OCTOBER 31, 2003 at 11.59PM PST (US). FULL PAPERS are due on November 7, 2003 at 11.59PM PST (US). NO EXTENSION WILL BE GRANTED!!! NOTIFICATION of acceptance/rejection will be given on FEBRUARY 17, 2004. FINAL VERSIONS of the accepted papers are due on MARCH 24, 2004.
As in previous years, a series of tutorials and workshops will be held immediately preceding the symposium. Tutorial and workshop proposals will be accepted until November 14, 2003. If you wish to organize a tutorial (1/2 or 1 day), e-mail a proposal to the Tutorials Chair (Timothy Pinkston, tpink@charity.usc.edu), including title, brief description of topics to be covered, and bio of the speakers. If you wish to organize a workshop (1 or 2 days), e-mail a proposal to the Workshops Chair (Sally A. McKee, sam@csl.cornell.edu), including title, brief description of topics to be covered, and bio of the organizers. Notification of tutorial and workshop decisions will be emailed back to authors on December 15, 2003.
Summary of important dates:
Abstract submission deadline: Oct 31, 2003
Paper submission deadline: Nov 7, 2003
Workshop/tutorial proposal deadline: Nov 14, 2003
Workshop/tutorial proposal notification: Dec 15, 2003
Paper acceptance notification: Feb 17, 2004
Final paper due: Mar 24, 2004
Please refer to http://isca.in.tum.de for the complete call for papers and other details about the symposium.
2nd CALL FOR PAPERS
Workshop on Network Processors & Applications - NP3
http://www.cse.wustl.edu/NP3/
February 14-15, 2004
Madrid, Spain
Held in conjunction with HPCA 10 - The 10th International
Symposium on High-Performance Computer Architecture
http://www.ac.uma.es/hpca10/
February 14-18, 2004
OVERVIEW
As the performance and importance of digital communication networks have increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility and economy requirements, the networking industry has opted to build products around network processors. These processors are programmable yet application-specific; their designs are tailored to efficiently implement communications applications such as: routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. The term network processor is used here in the most generic sense -- from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors.
Network processor design is an emerging field with numerous challenges and opportunities. The goal of this workshop is to provide a forum for engineers and scientists from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. We are especially interested in attracting new or experimental techniques and approaches.
IMPORTANT DATES
Submissions due: November 3
Author notifications: December 22
Final papers due: January 9
TOPICS
Topics of particular interest include, but are not limited to:
The workshop will consist of a keynote address, paper presentations and a panel session. In addition to academic and research contributions, product descriptions that focus on architecture (hardware or software) or performance analysis will also be considered. Attendees will receive a copy of workshop papers.
SUBMISSIONS
Please submit full papers (single spaced, font size 11, 1 inch margins, not exceeding 15 pages) in Adobe PDF format for review to pcrowley@cse.wustl.edu.
PROGRAM COMMITTEE
Alan Berenbaum, Agere
Brad Calder, UCSD
Andrew Campbell, Columbia University
Patrick Crowley, Washington University in St. Louis
Jordi Domingo, UPC (Spain)
Mark Franklin, Washington University in St. Louis
Jorge Garcia, UPC (Spain)
Haldun Hadimioglu, Polytechnic University
Marco Heddes, Transwitch Corporation
Manolis Katevenis, University of Crete (Greece)
Bill Mangione-Smith, UCLA
Kenneth Mackenzie, Reserviour Labs
John Marshall, Cisco
Daniel Mlynek, EPFL (Switzerland)
Peter Z. Onufryk, IDT
Lothar Thiele, ETH Zürich (Switzerland)
Jon Turner, Washington University in St. Louis
Mateo Valero, UPC (Spain)
Tilman Wolf, University of Massachusetts
ORGANIZERS
Patrick Crowley, Washington University in St. Louis (pcrowley@cse.wustl.edu) Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu) Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu) Peter Z. Onufryk, IDT (peter.onufryk@idt.com)
NP2 at HPCA 9 (2003)
http://www.cs.washington.edu/NP2/
Selected papers from NP2 and additional industry contributions will appear in Network Processor Design : Issues and Practices Volume II (Morgan Kaufmann Publishers, October 2003).
NP1 at HPCA 8 (2002)
http://www.cs.washington.edu/NP1/
Selected papers from NP1 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume I http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-875-3 (Morgan Kaufmann Publishers, September 2002).
The 11th Reconfigurable Architectures Workshop (RAW 2004) will be held at the Eldorado Hotel Santa Fe, New Mexico on Monday, April 26, and Tuesday April 27 2004. RAW 2004 is associated with the 18th Annual International Parallel and Distributed Processing Symposium (IPDPS 2004) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. RAW 2004 is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
The main focus of the workshop is on
Run-Time & Dynamic Reconfiguration: Architectures, Algorithms, Technologies
Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-grain FPFAs) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2004 aims to provide a forum for creative and productive interaction between all these disciplines.
Topics of Interest:
Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to:
Models & Architectures
Algorithms & Applications
Technologies & Tools
Submission Guidelines:
Authors should submit by email an electronic version of their work by
October 20, 2003 to Serge Vernalde, IMEC, Belgium (vernalde@imec.be) AND
register their paper through our web-interface at
http://www.ece.lsu.edu/vaidy/raw04/
All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 pages of single spaced text, including figures and tables) or, in special cases, may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Authors should make sure that the submission can be viewed using ghostscript and will print on standard letter size paper (8.5" x 11").
The IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk.
Important Dates:
Manuscript due: October 20, 2003 Notification of acceptance/rejection: November, 2003 Final version due: January, 2004
Organization:
Workshop Chair: Juergen Becker, Universitat Karlsruhe (TH), Germany
(becker@itiv.uni-karlsruhe.de) Program Chair: Serge Vernalde, IMEC, Belgium
(vernalde@imec.be)
Steering Chair: Viktor K. Prasanna, University of Southern California, USA
(prasanna@ganges.usc.edu) Publicity Chair (USA): Ramachandran Vaidyanathan, Louisiana State
University, USA
(vaidy@ece.lsu.edu)
Publicity Chair (Europe, Asia): Reiner Hartenstein, Kaiserslautern University
of Technology, Germany
(reiner@hartenstein.de)
Program Committee:
Jeffrey Arnold, Adaptive Silicon, Inc., USA
Juergen Becker, Universitat Karlsruhe (TH), Germany
Neil Bergmann, University of Queensland, Australia
Christophe Bobda, Universitat Erlangen-Nurnberg, Germany
Don Bouldin, University of Tennessee, USA
Gordon Brebner, University of Edinburgh, UK
Klaus Buchenrieder, Infineon Technologies, Germany
Thomas Buchner, IBM, Germany
Peter Y. K. Cheung, Imperial College of Science Technology & Medicine, London,
UK
Oliver Diessel, University of New South Wales, Australia
Carl Ebeling, University of Washington, USA
Hossam ElGindy, University of New South Wales, Australia
Manfred Glesner, Darmstadt University of Technology, Germany
Patrick Girard, LIRMM, Montpellier, France
Steve Guccione, Quicksilver Technology, USA
Herbert Gruenbacher, Vienna University of Technology, Austria
Wolfram Hardt, Technische Universitat Chemnitz, Germany
Reiner Hartenstein, University of Kaiserslautern, Germany
Ulrich Heinkel, Lucent Technologies, Germany
Mark Jones, Virginia Tech, USA
Mohammed A. S. Khalid, Cadence Design Systems, USA
Hyoung-Joong Kim, Kangwon National University, Korea
Fabrice Kordon, Université Pierre & Marie Curie, Paris, France
Rainer Kress, Infineon Technologies, Germany
Markus Kuehl, Forschungszentrum Informatik (FZI), Karlsruhe, Germany
Rudy Lauwereins, IMEC, Leuven, Belgium
Philip Leong, Chinese University of Hong Kong, China
Marnane Liam, University College, Ireland
Rong Lin, State University of New York, Geneseo, USA
Wayne Luk, Imperial College, UK
Juergen Luka, DaimlerChrysler AG, Germany
Patrick Lysaght, Xilinx, USA
Malgorzata Marek-Sadowska, University of California, Santa Barbara, USA
John McHenry, National Security Agency, USA
Alessandro Mei, University Rome "La Sapienza", Italy
Martin Middendorf, Katholische Universität Eichstätt, Germany
Amar Mukherjee, University of Central Florida, USA
Dietmar Meuller, Technische Universitat Chemnitz, Germany
Koji Nakano, Hiroshima University, Japan
Marco Platzner, Swiss Federal Institute of Technology (ETH) Zuerich,
Bernard Pottier, Université de Bretagne Occidentale, France
Ranjani Parthasarathi, School of Computer Science and Engineering,
Anna University, Chennai, India
Michel Renovell, LIRMM, France
Franz Rammig, Universitat Paderborn, Germany
Peter Roth, IBM, Germany
Sakir Sezer, Queen's University, N. Ireland, U.K.
John Schewel, Virtual Computer Corp., USA
Hartmut Schmeck, Universität Karlsruhe (TH), Germany
Gerard Smit, University of Twente, The Netherlands
V. Sridhar, Satyam Computer Services Ltd., India
Juergen Teich, Friedrich-Alexander-Universitaet Erlangen, Germany
Lionel Torres, LIRMM, Montpellier, France
Jim Torresen, University of Oslo, Norway
Jerry L. Trahan, Louisiana State University, USA
Ramachandran Vaidyanathan, Louisiana State University, USA
Milan Vasilko, Bournemouth University, UK
Stamatis Vassiliadis, Delft University of Technology, The Netherlands
Serge Vernalde, IMEC, Belgium
Martin Vorbach, PACT Informationstechnologie, Germany
K. Waldschmidt, Universitat Frankfurt, Germany
Norbert Wehn, University of Kaiserslautern, Germany
Peixin Zhong, Lucent Technologies, USA
Hans Christoph Zeidler, Universitat der Bundeswehr Hamburg, Germany
WEPA-1: 1st Workshop on Embedded Parallel Architectures
(dragon.kayamba.com/~enric/wepa-1.htm)
to be held in conjunction with the
10th International Symposium on High Performance Computer
Architecture
Madrid, Spain
Saturday, Feb 14th, 2004
Objectives and Scope
The workshop addresses the different issues encountered while architecting parallel systems (multi-processor, multi-threaded, hybrid) for embedded applications.
The workshop papers will explore the issues at the architecture level, the support needed at the compiler and OS, the effort placed at the application level in porting old code to the new architectures and the tools developed to simulate the performance of the embedded systems.
The goal of this workshop is to create a forum wherein the authors can present the issues they have encountered and the solutions they have applied in order to solve the problems. Papers submitted to WEPA-1 must contain new research or improvement on previous works that have not been already presented in a prior conference.
Major topics include, but are not limited to
Workshop Co-chairs
Important Deadlines
Questions and Submission Procedure
Eldorado Hotel - Santa Fe, New Mexico
October 27, 2003
HAPCW 2003 will be held on October 27, 2003 in conjunction with the 2003 Los Alamos Computer Science Institute Symposium 2003 (LACSI2003), at the Eldorado Hotel in Santa Fe, New Mexico. High Availability (HA) Computing has long been played a critical role in industry mission critical applications. On the other hand, High Performance Computing (HPC) has equally been a significant enabler to the R&D community for their scientific discoveries. With combination of HA and HPC, together will clearly lead to even more benefits to both industry, academic and research entities.
HAPCW2003 will provide an important venue for discussing state-of-art and on-going research and development in HAPC. In addition to the presentation of reviewed papers, the workshop will include a panel discussion of relevant topics.
September 22, 2003 Extended Abstract Due September 26, 2003 Acceptance Notification October 17, 2003 Final paper due (electronic copy) October 27, 2003 Workshop (HAPCW) at LACSI
Stephen L. Scott Chokchai (Box) Leangsuksun Computer Science & Mathematics Division Computer Science Department, Oak Ridge National Laboratory Louisiana Tech University Oak Ridge, TN 37831, USA Ruston, LA 71272, USA scottsl@ornl.gov box@latech.edu
HAPCW http://cenit.latech.edu/hapcw2003 October 27, 2003 LACSI http://lacsi.lanl.gov/symposium October 27-29, 2003
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Call For Papers
HiCOMB 2004 3rd International Workshop On High Performance Computational Biology
http://www.hicomb.org/
held in conjunction with the
International Parallel and Distributed Processing Symposium
www.ipdps.org
April 26, 2004
Eldorado Hotel, Santa Fe, NM
Computational Biology is fast emerging as an important discipline for academic research and industrial application. The large size of biological data sets, inherent complexity of biological problems and the ability to deal with error-prone data all result in large run-time and memory requirements. The goal of this workshop is to provide a forum for discussion of latest research in developing high-performance computing solutions to problems arising from molecular biology. We are especially interested in parallel algorithms, memory- efficient algorithms, large scale data mining techniques, and design of high-performance software. The workshop will feature contributed papers as well as invited talks from reputed researchers in the field. Topics of interest include but are not limited to:
Papers reporting on original research (both theoretical and experimental) in all areas of bioinformatics and computational biology are sought. Surveys of important recent results and directions are also welcome. To submit a paper, send a postscript or PDF copy of the paper by email to the workshop's Program Chair, Prof. Dan C. Marinescu, <dcm@cs.ucf.edu>. The paper should not exceed 12 single-spaced pages (US Letter or A4 size) in 11pt font or larger. All papers will be reviewed. IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press on CD-ROM and will also be available in the IEEE Digital Library.
Authors of selected papers from the workshop will be invited to submit extended versions of their papers for publication in the journal Concurrency and Computation: Practice and Experience.
December 1, 2003 Workshop paper due December 31, 2003 Author Notification January 23, 2004 Camera-ready Paper Due
Prof. Srinivas Aluru Prof. David A. Bader Electrical & Computer Engg. Electrical & Computer Engg. Iowa State University University of New Mexico 3218 Coover Hall Albuquerque, NM 87131 USA Ames, IA 50014 USA Email: dbader@ece.unm.edu Email: aluru@iastate.edu Tel: 505-277-6724
Tel: 515-294-3539
Phone: +1 407 823 4860 FAX: +1 407 823 5419
Prof. Alberto Apostolico
Computer Sciences Department
Purdue University
West Lafayette, IN, 47907
Email: axa@cs.purdue.edu
http://www.cs.purdue.edu/people/axa
Phone: +1.765.494.6015
Prof. Concettina Guerra
Dip. Ingegneria dell'Informazione
Universita'di Padova
via Gradenigo 6a, 35100, Padova, Italy
Email: guerra@dei.unipd.it
http://www.dei.unipd.it/~guerra
Phone: +39 049 827 7933
Prof. Wojciech Szpankowski
Computer Sciences Department
Purdue University
West Lafayette, IN, 47907
Email: spa@cs.purdue.edu
http://www.cs.purdue.edu/people/spa
Phone: +1.765.494.6703
--
Call For Papers
Workshop on Communication Architecture for Clusters (CAC '04)
To be held in Conjunction with
Int'l Parallel and Distributed Processing Symposium (IPDPS '04)
Santa Fe, New Mexico Eldorado Hotel, April 26-30, 2004
web page http://www.cis.ohio-state.edu/~cac
Call For Papers
THEME:
The availability of commodity PCs/workstations and high-speed networks (Local Area Networks and System Area Networks) at low prices enabled the development of low-cost clusters. These clusters are being targeted for support of traditional high-end computing applications as well as emerging applications, especially those requiring high-performance servers. Designing high-performance and scalable clusters for these emerging applications requires design and development of high-performance communication and I/O subsystems, low-overhead programming environment support and support for Quality of Service (QoS). New standards such as InfiniBand Architecture (IBA) and PCI Express AS, and availability of high-speed networking products (Myrinet, Quadrics, IBA 4X, and 10GigEthernet) are providing exciting ways to design high-performance communication and I/O architectures for clusters. A large number of research groups from academia, industry, and research labs are currently engaged in the above research directions. The goal of this workshop is to bring together researchers and practitioners working in the areas of communication, I/O, and architecture to discuss state-of-the-art solutions as well as future trends for designing scalable, high-performance, and cost-effective communication and I/O architectures for clusters. The first three workshops in this series (CAC '01, CAC '02, and CAC '03) were held in conjunction with IPDPS conferences, and they were very successful. The CAC '04 workshop plans to continue this tradition.
TOPICS OF INTEREST:
Topics of interest for the workshop include but are not limited to:
Router/switch, network, and network-interface architecture for supporting efficient point-to-point communication, collective communication, and I/O at intra-cluster and inter-cluster levels.
Design, development, and implementation of low-level communication and I/O protocols (GM, TCP/IP, VAPI, SDP, DAPL, SRP, iSCSI, RDMA over IP, etc) on different networking and interconnect technologies (such as Myrinet, 10Gigabit Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.). High-performance implementation of different programming layers (Message Passing Interface (MPI), Distributed Shared Memory such as TreadMarks, Get/Put, Global Arrays, sockets, etc.) and File Systems (such as PVFS and DAFS).
Communication and architectural issues related to switch organization, flow control, congestion control, routing and deadlock-handling, load balancing, reliability, and QoS support.
Strategies, algorithms, and protocols for management of communication resources, including topology discovery, hot update/replacement of components, dynamic reconfigurations, etc.
Performance evaluation and tools for different application areas, including interprocessor communication and I/O, etc. Results of both theoretical and practical significance will be considered.
PROCEEDINGS:
The proceedings of this workshop will be published together with the proceedings of other IPDPS '04 workshops by the IEEE Computer Society Press.
PAPER SUBMISSIONS:
We are planning a purely web submission and review process. Authors are requested to submit papers (in PDF format) not exceeding 10 single-spaced pages, including abstract, five key words, contact address, figures, and references. Detailed instructions on web submissions will be available soon.
Note: the PDF file must be viewable using the ``acroread'' tool. It is also important, when creating your PDF file, to use a page size of 8.5x11 inches (LETTER sized output not A4), since an A4 sized page may be truncated on a LETTER sized printer.
SCHEDULE:
Title and Abstract: October 30, 2003 Paper submission: November 3, 2003 Notification of acceptance: December 19, 2003 Camera-ready due: January 23, 2004
WORKSHOP CO-CHAIRS:
Dhabaleswar K. Panda (Ohio State), Jose Duato (Tech. Univ. of Valencia, Spain), and Craig Stunkel (IBM TJ Watson Research Center)
PROGRAM COMMITTEE:
Bulent Abali (IBM TJ Watson) Mohammad Banikazemi (IBM TJ Watson) Angelos Bilas (Univ. of Toronto, Canada) Alan Benner (IBM) Ron Brightwell (Sandia National Lab) Darius Buntinas (Argonne National Lab) Toni Cortes (UPC, Spain) Wu-Chun Feng (Los Alamos National Lab) Jose Flich (Tech. Univ. of Valencia, Spain) Mitchell Gusat (IBM, Zurich) Mark Heinrich (Univ. of Central Florida)
Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece) Nectarios G. Koziris (National Technical Univ. of Athens, Greece)
Mario Lauria (Ohio State) Olav Lysne (Univ. of Oslo, Norway) Arthur (Barney) Mccabe (Univ. of New Mexico) Pankaj Mehra (HP) Shubu Mukherjee (Intel) Jarek Nieplocha (Pacific Northwest National Lab) Scott Pakin (Los Alamos National Lab) Fabrizio Petrini (Los Alamos National Lab) Greg Pfister (IBM) Timothy Pinkston (Univ. of Southern California) Wolfgang Rehm (Tech. Univ. of Chemnitz, Germany) Antonio Robles (UPV, Spain) Tom Rokicki (Instantis) Reza Rooholamini (Dell) Evan Speight (Cornell Univ.) Thomas M. Stricker (ETH, Zurich, Switzerland) Peter Varman (NSF and Rice Univ.) Pete Wyckoff (Ohio Supercomputer Center) Mazin Yousif (Intel)
PUBLICITY COORDINATORS:
Darius Buntinas (Argonne National Lab) and Nectarios G. Koziris (National Technical Univ. of Athens, Greece)
ADDITIONAL INFORMATION:
For further questions, send e-mail to cac@cis.ohio-state.edu.
Workshop on Interaction between Compilers and Computer Architectures (Interact 8)
http://api.ece.uic.edu/workshop/interact.htm
February 15, 2004
Madrid, Spain
Held in Conjunction with HPCA 10
http://www.ac.uma.es/hpca10/
IMPORTANT DATES
Submissions due: November 23, 2003
Acceptance notification by December 22, 2003
Final version due by January 12, 2004
TOPICS
Program Committee Chair:
Wei Hsu (U. Minnesota)
Program Committee:
Sangyeun Cho (Samsung Electronic)
Dan Conners (U. Colorado)
Antonio Gonzalez (UPC Spain)
Rick Hank (Hewlett Packard)
Allan Knies (Intel)
Gyungho Lee (UI-Chicago)
Sally McKee (Cornell University)
Sanjay Patel (UI-Urbana-Champaign)
Eric Rotenberg (NC State)
Zhao Zhang (Iowa State University)
Formal post-workshop proceedings will be published by IEEE Computer
Society
Press. An informal collection of the papers to be presented will be
distributed at the workshop. Questions regarding the post-workshop
proceedings
should be forwarded to ghlee@ece.uic.edu.
For more details, visit
http://api.ece.uic.edu/workshop/interact.htm