Welcome to IEEE TCCA Email-Monthly, Oct. 2005.

1. SBAC-PAD 2005: 17th International Symposium on Computer Architecture

   and High Performance Computing *October 24-27, 2005, Copacabana, Rio de Janeiro *Call for Participation: http://www.sbc.org.br/sbac/2005 *Submitted by Mario João Junior <junior@nce.ufrj.br>

2. Computer Architecture Letters announces our most recent papers

   *Website: http://www.comp-arch-letters.org *Submitted by: Kevin Skadron <skadron@cs.virginia.edu>

3. PACT06: 2006 IEEE/ACM/IFIP International Conference on

   Parallel Architectures and Compilation Techniques *September 16-20, 2006, Seattle, Washington *Call for Papers: http://www.pactconf.org *Submitted by: Kevin Skadron <skadron@cs.virginia.edu>

4. HiPEAC 2005 Conference

   *17-18 November 2005, Barcelona, right after MICRO-38 *Early registration and student discounts: October 12 *CALL FOR PARTICIPATION http://www.hipeac.net/hipeac2005

5. ICPADS 2006: International Conference on Parallel and Distributed Systems

   *July 12-15, 2006, Minneapolis, Minnesota *Paper Submission: January 15, 2006 *CALL FOR PAPERS http://www.icpads.umn.edu/ *Submitted by Nian-Feng Tzeng <tzeng@cacs.louisiana.edu>

6. IPDPS 2006: 20th IEEE International Parallel & Distributed Processing

   Symposium *APRIL 25-29, 2006, RHODES ISLAND, GREECE *Paper submission deadline: Friday, October 14, 2005 at 5pm EDT *Submitted by Roy S.C. Ho <scho@cs.hku.hk> *CALL FOR PAPERS: www.ipdps.org

7. WMPI2006: The Fourth Workshop on Memory Performance Issues

   *Held in conjunction with the 12th HPCA, Austin, Texas, Feb., 2006 *Submission due: Dec. 2, 2005, 10 PST (firm deadline) *Call For Papers: http://www.cs.utah.edu/wmpi/2006/ *Submitted by Liqun Cheng <legion@cs.utah.edu>

        send an email to
                qyang@ele.uri.edu

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  Call for Participation

SBAC-PAD 2005
17th International Symposium on Computer Architecture and High Performance Computing Copacabana, Rio de Janeiro, October 24-27, 2005

http://www.sbc.org.br/sbac/2005

SBAC-PAD 2005 will be held at Hotel Pestana, Copacabana, Rio de Janeiro, from 24th to 27th October 2005. SBAC-PAD is an international conference that traditionally presents an overview of new developments and trends in computer architecture, parallel and distributed technologies and applications for high performance computing.

This year, 29 high quality papers from 83 submissions were accepted for publication, with 13 of these papers being among 33 international submissions received from 18 different countries. The areas of the selected papers range from Computer Architecture and System Software, to Algorithms and Applications and will cover topics in all areas of interest to SBAC-PAD, including:

• Application-specific Architectures;
• Cache and Memory Architectures;
• Fault-Tolerant Architectures and Systems;
• Grid, Cluster, Pervasive and Heterogeneous Computing;
• High Performance Applications;
• Languages, Compilers and Tools for Parallel and Distributed Programming;
• Load Balancing and Scheduling;
• Operating Systems;
• Processor Microarchitectures;
• Parallel and Distributed Algorithms, Architectures, Interconnection Networks, Routing and Communication;
• Benchmarking, Performance Measurements and Analysis;
• Reconfigurable Systems.

Paper presentations will be distributed over 10 sessions during all 4 conference days. The program also includes 4 keynote speakers and 2 timely tutorials. The keynote speeches will be given by Prof. Gurindar Sohi, University of Wisconsin-Madison, USA; Prof. Ronald H. Perrott, Queen´s University of Belfast; Peter W. Haas, High Performance Computing Center Stuttgart, Germany and Prof. Constantino Tsallis, CBPF, Brazil and Santa Fe Institute, USA.

The selected tutorials are "Design of Application Specific Processors", to be presented by Prof. Rainer Leupers of the Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany, and "Accelerated Development of Grid Applications", which will presented by Prof. Artur Andrzejak from the Zuse Institute, Berlin, Germany.

SBAC-PAD 2005 will have also an exciting social program in Rio, including sightseeing, a cocktail and a gala dinner. SBAC-PAD 2005 welcomes and invites researchers, developers, faculty members and students around the world to participate in the symposium. For registration and other information, please visit the SBAC-PAD 2005 home page at http://www.sbc.org.br/sbac/2005.
We are looking forward to welcoming you in Rio de Janeiro, Brazil, this October.

General Chair:

Gabriel P. Silva
Universidade Federal do Rio de Janeiro

Vice-Chair:

Vinod Rebello
Universidade Federal Fluminense

Program Chairs:

Claudio L. Amorim
Universidade Federal do Rio de Janeiro
Jack Dongarra
University of Tennessee

Program Committee:

Alberto F. de Souza (Brazil)
Alfredo Goldman (Brazil)
Alvaro L. G. A. Coutinho (Brazil)
Bertil Folliot (France)
Celso L. Mendes (USA)
Cesar A. F. De Rose (Brazil)
Christophe Cérin (France)
Claudio F. R. Geyer (Brazil)
Claudio L. Amorim (Brazil)
David Kaeli (USA)
Denis Trystram (France)
Edil S. T. Fernandes (Brazil)
Edson N. Cáceres (Brazil)
Eduardo W. Bergamini (Brazil)
Evangelos Markatos (Greece)
Felipe M. G. França (Brazil)
Frank Dehne (Canada)
Gabby Silberman (USA)
Guido Araújo (Brazil)
Hans-Ulrich Heiss (Germany)
Horst D. Simon (USA)
H. J. Siegel (USA)
Jack Dongarra (USA)
Jairo Panetta (Brazil)
Jean-Luc Gaudiot (USA)
José Fortes (USA)
José H. Saito (Brazil)
José N. Amaral (Canada)
Kazuaki Murakami (Japan)
Kuan-Ching Li (Taiwan)
Laurence T. Yang (Canada)
Líria M. Sato (Brazil)
Liviu Iftode (USA)
Luiz DeRose (USA)
Manuel Lois Anido (Brazil)
Mario Nemirovsky (USA)
Mateo Valero (Spain)
Nader Bagherzadeh (USA)
Orlando G. Loques (Brazil)
Osni Marques (USA)
Philippe O. A. Navaux (Brazil)
Qing (Ken) Yang (USA)
Rafael D. Lins (Brazil)
Rajkumar Buyya (Australia)
Renato S. Silva (Brazil)
Ricardo Bianchini (USA)
Ron Perrott (North Ireland)
Ronaldo A. L. Gonçalves (Brazil)
Sérgio Bampi (Brazil)
Sérgio T. Kofuji (Brazil)
Siang W. Song (Brazil)
Tadao Nakamura (Japan)
Valmir C. Barbosa (Brazil)
Wagner Meira Jr. (Brazil)
Walfredo C. Cirne (Brazil)
Yale Patt (USA)

We are pleased to note that, beginning in 2006, Computer Architecture Letters will become on official publication of the IEEE, included in the IEEE digital library. We continue to seek new submissions and remain committed to fast yet accurate review. Our mean time to decision remains one month, with an acceptance rate of approximately 22%.

• N. Riley and C. Zilles. "Probabilistic Counter Updates for Predictor Hysteresis and Bias." Volume 4, Aug. 2005.
• H. Zhou. "A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors." Volume 4, Sep. 2005.
• M.-S. Lee, S.-K. Lee, J. Lee, S.-R. Maeng. "Adopting System Call Based Address Translation into User-Level Communication." Volume 4, Sep. 2005.

Abstracts

• N. Riley and C. Zilles. "Probabilistic Counter Updates for Predictor Hysteresis and Bias." Volume 4, Aug. 2005.

Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor designs are currently impractical because their counter tables are too large. We describe a method for dramatically reducing the amount of storage required for a predictor's counter table with minimal impact on prediction accuracy. Probabilistic updates to counter state are implemented using a hardware pseudo-random number generator to increment or decrement counters a fraction of the time, meaning fewer counter bits are required.

We demonstrate the effectiveness of probabilistic updates in the context of Fields et al.'s critical path predictor, which employs a biased 6-bit counter. Averaged across the SPEC CINT2000 benchmarks, our 2-bit and 3-bit probabilistic counters closely approximate a 6-bit deterministic one (achieving speedups of 7.75% and 7.91% compared to 7.94%) when used for criticalitybased scheduling in a clustered machine. Performance degrades gracefully, enabling even a 1-bit probabilisitic counter to outperform the best 3-bit deterministic counter we found.

• H. Zhou. "A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors." Volume 4, Sep. 2005.

This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent latency-tolerance proposal, dual-core execution (DCE). In DCE, a program is executed twice in two processors, named the front and back processors. The front processor pre-processes instructions in a very fast yet highly accurate way and the back processor re-executes the instruction stream retired from the front processor. The front processor runs faster as it has no correctness constraints whereas its results, including timely prefetching and prompt branch misprediction resolution, help the back processor make faster progress. In this paper, we propose to entrust the speculative results of the front processor and use them to check the un-speculative results of the back processor. A discrepancy, either due to a transient fault or a mispeculation, is then handled with the existing mispeculation recovery mechanism. In this way, both transient-fault tolerance and performance improvement can be delivered simultaneously with little hardware overhead.

• M.-S. Lee, S.-K. Lee, J. Lee, S.-R. Maeng. "Adopting System Call Based Address Translation into User-Level Communication." Volume 4, Sep. 2005.

User-level communication alleviates the software overhead of the communication subsystem by allowing applications to access the network interface directly. For that purpose, efficient address translation of virtual address to physical address is critical. In this study, we propose a system call based address translation scheme where every translation is done by the kernel instead of a translation cache on a network interface controller as in the previous cache based address translation. According to our experiments, our scheme achieves up to 4.5 % reduction in application execution time compared to the previous cache based approach.

Call for Papers
2006 IEEE/ACM/IFIP International Conference on Parallel Architectures and Compilation Techniques

http://www.pactconf.org

PACT is a multi-disciplinary conference that brings together researchers from the hardware and software areas to present ground-breaking research in architecture, compilation, applications, and languages related to parallel systems ranging across instruction-level parallelism, thread-level parallelism, multiprocessor parallelism and distributed systems.

PACT features cutting-edge research in architecture, compilers, languages and applications across a broad range of topics, including, but not limited to:

• Parallel architectures and computational models
• Compilers and tools for parallel computer systems
• Superscalar, VLIW, multicore, and multithreaded architectures
• Compiler/hardware support for hiding memory latencies
• Hardware and software support for energy/thermal-aware computing
• Hardware and software for network processing
• Reconfigurable computing
• Dynamic translation and optimization
• I/O issues in parallel computing and their relation to applications
• Parallel programming languages, algorithms and applications
• Run time system support for parallel systems
• Mobile/wireless computing for parallel applications
• Application specific systems
• Applications and experimental systems studies
• Parallel processing in type safe languages (Java, C#, etc.)
• Non-traditional computing systems topics
• Support for correctness in hardware and software (esp. with concurrency)

Sponsored by ACM, IEEE Computer Society, and IFIP WG 10.3

*Important Deadlines

    Abstract Submission          Monday, March 27, 2006
    Full Paper Submission        Monday, April 3, 2006
    Conference                   September 16-20, 2006

*Information for Authors
The abstract submission includes a description (100-300 words) of the paper and an indication of the key topics of the paper. The abstract deadline for submissions is March 27, 2006. The paper deadline for submissions is one week later, April 3, 2006. NO EXTENSIONS WILL BE GRANTED!.

Your paper should be formatted in PDF format for letter-size paper. Submissions must be viewable by Adobe Acrobat Reader (version 4.0 or higher). Your submission may not exceed 10 pages of conference two column paper format using 10pt fonts. The program chair will summarily return submissions exceeding this page limit.

*Tutorials and Workshops
Proposals are solicited for tutorials and workshops to be held during the conference. Interested individuals are invited to submit proposals to the Workshops chair, Albert Cohen (Albert dot Cohen at inria dot fr), and the Tutorials Chair, Sandhya Dwarkadas (sandhya at cs dot rochester dot edu).

*Organizing Committee

General Chair

Erik Altman, IBM Research
Program Chairs

Kevin Skadron, U. Virginia
Ben Zorn, Microsoft Research
Local Arrangements Chair

Trishul Chilimbi, Microsoft Research Publicity Co-Chairs

Americas: Jack Davidson, U. Virginia Europe: Jens Knoop, TU Vienna
Asia/Pacific: R. Govindarajan, IISc Bangalore Workshops Chair

Albert Cohen, INRIA
Tutorials Chair

Sandhya Dwarkadas, U. Rochester
Publications Chair

Sudhanya Gurumurthi, U. Virginia
Web Chair

Hillery Hunter, IBM Research
Submissions Chair

Jeremy Sheaffer, U. Virginia
Registration Chair

Michael Gschwind, IBM Research
Finance Chair

Lixin Zhang, IBM Research

Program Committee

Ali-Reza Adl-Tabatabai, Intel
David August, Princeton U.
Rajeev Barua, U. Maryland
Frank Bellosa, U. Karlsruhe
Steve Blackburn, Intel
Brad Calder, UC San Diego
Jacqueline Chame, ISI
Fred Chong, UC Santa Barbara
Michel Cosnard, INRIA & UNSA
Bronis de Supinski, LLNL
Jim Dehnert, Google
Chen Ding, U. Rochester
Paraskevas Evripidou, U. Cyprus
Jean-Luc Gaudiot, UC Irvine
R. Govindarajan, Indian Inst. Of Sci., Bangalore Sudhanva Gurumurthi, U. Virginia
Kim Hazelwood, U. Virginia
Michael Hind, IBM Research
David Koppelman, Lousiana State U.
Christos Kozyrakis, Stanford U.
Josep-L. Larriba-Pey, U. Politécnica Catalunya John Mellor-Crummey, Rice U.
Maged Michael, IBM Research
Erez Petrank, Technion, Israel
Keshav Pingali, Cornell U.
Partha Ranganathan, Hewlett-Packard Labs Glenn Reinman, UC Los Angeles
Gabriel Silberman, CA Labs
Yuanyuan Zhou, U. Illinois

Steering Committee

Gabriel Silberman, CA Labs, Chair
Michel Cosnard, INRIA & UNSA
Kemal Ebcioglu, IBM
Ulrich Finger, EURECOM
Jean-Luc Gaudiot, UCI
David Kaeli, Northeastern
David Koppelman, Louisiana State
Josep-L. Larriba-Pey, UPC
Kathryn McKinley, U. Texas
Josep Torrellas, U. Illinois
Mateo Valero, UPC

Apply to early registration and student discounts before October 12!

The program ( http://www.hipeac.net/hipeac2005/index.php?page=program ), with contributions by authors from nine countries, presents important results in a wide range of areas, including analysis and evaluation techniques, novel memory and interconnect architectures, security architectures, novel compiler and runtime techniques, and domain specific architectures.

The keynotes will focus on the development of multicore processor benchmarks for embedded systems, and new opportunities and challenges for the chip-multiprocessing paradigm.

The Conference will take place at Barcelona Diagonal Mar, the totally renovated area of Barcelona on the Mediterranean Sea shore that hosted the 2004 Universal Forum of Cultures.

Registration, hotel, and program information for HiPEAC 2005 are now available at http://www.hipeac.net/hipeac2005

The conference organization is shared with MICRO-38. If you plan to attend both conferences you just need to make a reservation in one of the hotels for the whole period.
There is a limited number of grants that cover the full registration fee for students from HiPEAC institutions.

Looking forward to see you in Barcelona, HiPEAC 2005 Chairs

CALL FOR PAPERS

Twelfth International Conference on Parallel and Distributed Systems (ICPADS 2006)

               Minneapolis, Minnesota
                     July 12-15, 2006
            http://www.icpads.umn.edu/

PURPOSE AND SCOPE

The 2006 International Conference on Parallel and Distributed Systems (ICPADS 2006) provides an international forum for scientists, engineers, and users to exchange and share their experiences, new ideas, and latest research results on all aspects of parallel and distributed systems. All accepted papers will appear in the Proceedings of ICPADS 2006, which is to be published by the IEEE Computer Society Press. Awards will be given to the best papers. Topics of particular interest include, but are not limited to:

• Parallel and Distributed Architectures and Systems
• Parallel and Distributed Applications and Algorithms
• Distributed OS, Databases, and Resource Management
• Multi-core and Multithreaded Architectures
• Thermal Management and Power-Aware Computing
• Reliable and Fault-Tolerant Computing
• Grid, Peer-to-Peer, and Cluster Computing
• Web-based Computing and Services
• Wireless and Mobile Computing
• Ad Hoc and Sensor Networks
• Communication Networks and Protocols
• Interconnection Networks and I/O
• Real-Time and Multimedia Systems
• Security and Privacy
• Performance Modeling, Tools, and Evaluation

WORKSHOPS

The Twelfth International Conference on Parallel and Distributed Systems (ICPADS) (http://www.icpads.umn.edu/) will be held in Minneapolis during
July 12-15. Several one-day workshops are expected to be organized on July 15th,
on the last day of the conference. ICPADS workshops provide an opportunity to
discuss and explore emerging areas of parallel and distributed systems research with a group of like-minded researchers and practitioners. Workshops may focus on any aspect of parallel and distribued systems, established concerns, real-world advances, or new ideas. The goal of the workshops are to share understandings and experiences, to foster research communities, to learn from each other and to envision future directions.

Proposals for the workshops are solicited. Workshop proposals should be no longer than 2 pages, and should include a summary describing the theme(s) of the workshop, scope and motivation, topics of interest, brief biographies of the organizer(s), expected number of participants, and the means of soliciting participation. The proposals should be in PDF format and emailed to prasant@cs.ucdavis.edu.

IMPORTANT DATES

• Paper Submission: January 15, 2006
• Author Notification: April 1, 2006
• Final Manuscript(Camera-Ready Version): April 15, 2006
• Workshops Proposal Deadline: November 1, 2005
• Workshops: July 15, 2006
• Conference Dates: July 12-14, 2006

PAPER SUBMISSION

Papers representing original, unpublished work are invited to be submitted and will be evaluated based on originality, significance, technical soundness, and clarity of exposition. Submitted papers should be in single-column format with a minimal font-size of 11, and are not to exceed 5000 words (25 double-spaced pages) including figures and references. Please number each page. An abstract and 5-10 keywords should be included in each submission. Submissions will be handled via the conference web site at: http://www.icpads.umn.edu/submitpaper.htm

SPONSORED BY
The IEEE Computer Society Technical Committee on Parallel Processing. The IEEE Computer Society Technical Committee on Distributed Processing.

SPONSORED BY IEEE COMPUTER SOCIETY

SUBMISSION DEADLINE EXTENDED TO OCTOBER 14th

20th IEEE International Parallel & Distributed Processing Symposium Tuesday, 25 April - Saturday, 29 April 2006 Rodos Palace Resort Hotel & Convention Center Rhodes Island, Greece
www.ipdps.org

Sponsored by IEEE Computer Society Technical Committee on Parallel Processing
In cooperation with ACM SIGARCH, IEEE Computer Society Technical Committee on Computer Architecture, and IEEE Computer Society Technical Committee on Distributed Processing
Hosted by Research Academic Computer Technology Institute (CTI, Greece)

IPDPS 2006 CALL FOR PARTICIPATION
IPDPS serves as a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. The five-day program will follow the usual format of contributed papers, invited speakers, panels, and commercial participation mid week, framed by workshops held on the first and last days; this year in Greece that will be Tuesday and Saturday. Visit this Web site for regular updates, including the advance program, registration, and accommodations. Send general email inquiries to info@ipdps.org.

IMPORTANT DATES FOR IPDPS 2006
October 14, 2005 - Final Deadline for Manuscripts December 9, 2005 - Review Decisions Mailed January 21, 2006 - Camera-Ready Papers Due

IPDPS 2006 WORKSHOPS
Workshops are held on the first and last day of the symposium. Each workshop has its own requirements and schedule for submissions and all are linked from the IPDPS Web site. See list below of 20 workshops planned for 2006 in Greece. To link to an individual workshop site, visit: http://www.ipdps.org/ipdps2006/2006_workshops.html

GENERAL CO-CHAIRS
Paul Spirakis, CTI & University of Patras, Greece H.J. Siegel, Colorado State University, USA GENERAL VICE-CHAIRS
Sotiris Nikoletseas, CTI & University of Patras, Greece Charles Weems, University of Massachusetts Amherst, USA PROGRAM CHAIR
Arnold L. Rosenberg, University of Massachusetts Amherst, USA

IPDPS 2006 CALL FOR PAPERS
Authors are invited to submit manuscripts that present original unpublished research in all areas of parallel and distributed processing, including the development of experimental or commercial systems. Work focusing on emerging technologies is especially welcome. Topics of interest include, but are not limited to: - Parallel and distributed algorithms, focusing on issues such as:

stability, scalability, and fault tolerance of distributed systems, communication and synchronization protocols, network algorithms, and scheduling and load balancing.
- Applications of parallel and distributed computing, including web applications, peer-to-peer computing, grid computing, scientific applications, and mobile computing.
- Parallel and distributed architectures, including shared memory, distributed memory (including petascale system designs, and architectures with instruction-level and thread-level parallelism), special-purpose models (including signal and image processors, network processors, other special purpose processors), nontraditional processor technologies, network and interconnect architecture, parallel I/O and storage systems, system design issues for low power, design for high reliability, and performance modeling and evaluation. - Parallel and distributed software, including parallel programming languages and compilers, runtime systems, operating systems, resource management, middleware, libraries, data mining, and programming environments and tools.

HCW
Heterogeneous Computing Workshop
WPDRTS
Workshop on Parallel and Distributed Real-Time Systems RAW
Reconfigurable Architectures Workshop
HIPS
Workshop on High-Level Parallel Programming Models & Supportive Environments
JAVAPDC
Java for Parallel and Distributed Computing Workshop NIDISC
Workshop on Nature Inspired Distributed Computing HiCOMB
Workshop on High Performance Computational Biology APDCM
Advances in Parallel and Distributed Computing Models CAC
Communication Architecture for Clusters NSFNGS
NSF Next Generation Software Program
HPPAC
High-Performance, Power-Aware Computing PDSEC
Workshop on Parallel and Distributed Scientific and Engineering Computing WMPP
Workshop on Massively Parallel Processing PMEO
Performance Modelling, Evaluation, and Optimisation of Parallel and Distributed Systems
HPGC
High Performance Grid Computing
DPDNS
Dependable Parallel, Distributed and Network-Centric Systems SSN
International Workshop on Security in Systems and Networks SMTPS
Workshop on System Management Tools for Large-Scale Parallel Systems HOTP2P
International Workshop on Hot Topics in Peer-to-Peer Systems POHLL
Workshop on Performance Optimization for High-Level Languages and Libraries

• AMERICAS Bo Hong, Drexel University, USA
• ASIA/PACIFIC RIM Cho-Li Wang, University of Hong Kong, China
• EUROPE/AFRICA Ioannis Chatzigiannakis, Computer Technology Institute, Greece

STEERING COMMITTEE
David A. Bader, Georgia Institute of Technology, USA Luc Bougé, ENS Cachan & IRISA, Rennes, France K. Mani Chandy, California Institute of Technology, USA Jean-Luc Gaudiot, University of California, Irvine, USA Ali R. Hurson, Pennsylvania State University, USA Joseph JaJa, University of Maryland, USA F. Tom Leighton, MIT, USA
Sotiris E. Nikoletseas, CTI & University of Patras, Greece Co-Chair: Viktor K. Prasanna, University of Southern California, USA José D.P. Rolim, University of Geneva, Switzerland Arnold L. Rosenberg, University of Massachusetts Amherst, USA Sartaj Sahni, University of Florida, USA Behrooz Shirazi, University of Texas at Arlington, USA H. J. Siegel, Colorado State University, USA Paul Spirakis, CTI & University of Patras, Greece Hal Sudborough, University of Texas at Dallas, USA Charles Weems, University of Massachusetts Amherst, USA

Co-Chair: George B. Westrom, Future Scientists & Engineers of America, USA

WMPI-2006 Call For Papers
The Fourth Workshop on Memory Performance Issues Held in conjunction with the
12th International Symposium on High-Performance Computer Architecture (HPCA) Austin, Texas
February, 2006
http://www.cs.utah.edu/wmpi/2006/

Submission due: Dec. 2, 2005, 10 PST (firm deadline) Author notification: Jan. 6, 2006
Final paper due: Jan. 18, 2006

WMPI is a one-day workshop that provides a forum for researchers and practitioners from academia and industry to discuss advances in computer technology, architecture, software systems, and algorithms that address the growing disparity between processor and memory/network speeds. Hardware and software mechanisms that address this performance gap are equally welcome. We are particularly interested in new or controversial ideas. Work in early stages of development is encouraged. The workshop will include one or more keynote speakers. The best five to seven papers of this workshop will be published in a special issue of SIGMICRO newsletter.

Possible topics for papers include, but are not limited to, the following: Emerging RAM technologies (e.g., MRAM, nanotechnology, quantum devices) Exploiting processing capability in the memory system Intelligent memory and/or disk systems Reconfigurable memory systems
Memory systems for vector/stream architectures Memory-latency-hiding techniques
Memory-access-reducing techniques
Memory system design for large-scale supercomputers Memory-oriented speculation/prediction mechanisms Cache hierarchy organization
Scalable cache coherence mechanisms
Chip multiprocessor cache/memory designs Low-power memory systems
Embedded memory systems
Fault tolerant memory systems
Operating system memory management
Memory-aware compilation techniques
Memory-aware algorithm design

Please submit your paper before the due date for review by committee. Authors of accepted papers will present their work. Proceedings containing all papers will be provided to all attendees. Please make sure that your paper: is in PS or PDF format,
should not exceed 4,000 words and 8 pages, is formatted for printing on LETTER size paper, and is formatted for black-and-white printers (not color printers).

The deadline for submission is Dec 2, 2005 (no extension will be granted due to the short review period). Authors will be notified of the decision Jan 6, 2006. Final paper is due Jan 18, 2006.