Acheiving Typical Delays in 
Synchronous Systems via 
Timing Error Toleration

Augustus K. Uht
Department of Electrical and Computer Engineering
Kelley Hall
Univ. of Rhode Island
Kingston, RI 02881, USA

This paper introduces a hardware method of improving the performance of any synchronous digital system. We exploit the well-known observation that typical delays in synchronous systems are much less then the worst-case delays usually designed to, typically by factors of two or three or more. Our proposed family of hardware solutions employs timing error toleration (TIMERRTOL) to take advantage of this characteristic. Briefly, TIMERRTOL works by operating the system at speeds corresponding to typical delays, detecting when timing errors occur, and then allocating more time for the signals to settle to their correct values. The reference paths in the circuitry operate at lower speeds so as to always exhibit correct values (worst-case delays). The nominal speedups of the solutions are the same as the ratio of worst-case to typical delays for the application system. The increases in cost and power dissipation are reasonable. We present the basic designs for a family of three solutions, and examine and test one solution in detail; it has been realized in hardware. It works, and exhibits substantially improved performance. (Patent applied for.)