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Workshop on Computer Architecture Research
Directions |
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CARD 2007 |
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Held in conjunction with the 13th
Annual IEEE/ACM International Symposium on High-Performance Computer
Architecture |
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The CARD
2007 panel video and audio files are available for each of the four
mini-panels. Click to
DOWNLOAD PANEL VIDEOS Description |
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Decreasing transistor feature sizes simultaneously offer
increased opportunities and challenges for computer architecture researcher
and designers. With hundreds of millions or billions of transistors, computer
architects can propose complex microarchitectural enhancements, increase
processor functionality, or implement multiple processors-per-chip. On the
other hand, among other problems, shrinking transistor widths also lead to
increased static power dissipation; higher power densities, which require
active thermal management; and decreased reliability (due to soft-errors and
circuit degradation). The future directions of such open research problems are
unclear. The traditional way to tackle open research problems is for experts
in the field to write papers and present those papers in conferences. After
each presentation, other experts may ask one or two detailed questions that
are often too complex and assume too much background knowledge for many
audience members. After the session, the experts may assemble to discuss
finer points, reach some consensus and then go off to their respective bases
to do the next generation of research to write the next paper. While such a model is fine for the experts, it often is
not very helpful to an average audience member. Instead, a direct discussion
between experts would be far more useful. Such a discussion, properly
moderated by another expert, could quickly focus in on what are accepted
results and parameters of the subject, what are the open questions and areas
of disagreement of the subject and what are the most promising approaches to
those open problems. Audience questions, properly filtered by the moderator
to ensure relevance, would further guide the discussion. Accordingly, the purpose of this workshop is to serve as
a forum in which experts in each field can debate the state of the field and
future directions. The format is designed to quickly focus on areas of
disagreement, rather than expounding on areas of agreement which, presumably,
have ceased to be controversial, at least between the two panelists. The hope is that the workshop will be useful to a
diverse audience from a graduate student looking for good thesis topic areas
to a senior researcher who wants to hear the opinions of other area experts. More specifically, this workshop consists of following
four 60 minute mini-panels: |
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TIME |
Mini-Panel |
Moderator |
Panelists |
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1:00pm-1:01pm |
Opening
Remakrs |
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1:01pm-2:01pm |
Joel Emer Intel |
Yale Patt University of Texas |
Mark Hill University of Wisconsin |
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2:01pm-2:15pm |
Break |
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2:15pm-3:15pm |
Antonio Gonzalez Intel and UPC-Barcelona |
Shubhendu Mukherjee Intel |
Scott Mahlke University of Michigan |
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3:15pm-3:30pm |
Break |
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3:30pm-4:30pm |
Shay Gueron University of Haifa and Intel |
Geoffrey Strongin AMD |
Jean-Pierre Seifert University of Innsbruck |
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4:30pm-4:45pm |
Break |
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4:45pm-5:45pm |
University of Virginia |
Pradip Bose IBM |
Kanad Ghose SUNY-Binghamton |
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5:45pm-5:55pm |
Closing Remarks |
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Click
on each topic for the panelists’ and moderator’s position statements. |
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Organizers |
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University of Texas |
University of Rhode Island |
Freescale Semiconductor, Inc. |
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