The following is a partial list of papers relevant to the Levo project as of the date at the bottom of this page. All of these papers are on this CD, in the "papers" folder off of the root directory. The links below will take you right to them, and open them in Adobe Acrobat or your Postscript viewer, as appropriate. Most of the PDF files are Adobe Acrobat version 3.0 compatible.

SIGARCH-CAN'2002:

A. K. Uht. "Disjoint Eager Execution: What It Is / What It Is Not". SIGARCH Computer Architecture News, ACM, 30(1), March 2002. To appear. - PDF (208 KB) -

SSGRRw'2002:

A. K. Uht, S. Langford and D. Morano. "Interactive High-Performance Processor Understanding via the Web", (LevoVis paper). In Proceedings of the SSGRR 2002w International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, January 21 - 27, 2002, L'Aquila (Italy). - PDF (1 MB) -

PACT-WIP'2001:

A. K. Uht, D. Morano, A. Khalafi, M. de Alba, T. Wenisch, M. Ashouei and D. Kaeli. "Levo: IPC in the 10's via Resource Flow Computing". Presented at PACT 2001 Work-In-Progress (WIP) Session, September 2001. IEEE TCCA Newsletter, Special Issue, December 2001. - PDF (213 KB) -

URI-ELE-TR'2001-2:

A. K. Uht, D. Morano, A. Khalafi, M. de Alba, T. Wenisch, M. Ashouei and D. Kaeli. "IPC in the 10's via Resource Flow Computing with Levo". Technical Report No. 092001-001. Dept. of Electrical and Computer Engineering, University of Rhode Island, September 18, 2001. - PDF (328 KB) -

URI-ELE-TR'2001:

T. Wenisch and A. K. Uht. "HDLevo - VHDL Modeling of Levo Processor Components". Technical Report No. 072001-0100. Dept. of Electrical and Computer Engineering, University of Rhode Island, July 20, 2001. - PDF (332 KB) -

URI-ELE-TR'97-4:

A. K. Uht. "High Performance Memory System for High ILP Microarchitectures". Technical Report No. 0797-0002. Dept. of Electrical and Computer Engineering, University of Rhode Island, August 26, 1997. - Postscript (208 KB) -

URI-ELE-TR'97-2-A:

A. K. Uht. "Verification of ILP Speedups in the 10's for Disjoint Eager Execution". Technical Report No. 0697-0001, Rev. A. Dept. of Electrical and Computer Engineering, University of Rhode Island, July 11, 1997. - Postscript (1190 KB) -

COMPUTER'97:

A. K. Uht, V. Sindagi and S. Somanathan. "Branch Effect Reduction Techniques". COMPUTER, IEEE, 30(5):71-81, May, 1997. - PDF (375 KB) -

MICRO'95:

A. K. Uht and V. Sindagi. "Disjoint Eager Execution: An Optimal Form of Speculative Execution". In Proceedings of the 28th International Symposium on Microarchitecture (MICRO-28). ACM-IEEE, November/December 1995, pages 313-325. - Postscript (559KB) -

SIGARCH-CAN'93:

A. K. Uht. "Extraction of Massive Instruction Level Parallelism". ACM SIGARCH Computer Architecture News, 21(2 and 3), March and June 1993. - Postscript (192KB) -