Qing (Ken)
Yang 杨 庆
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Distinguished
Engineering Professor, Dept. of
Electrical and Computer Engineering, |
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Experiences |
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1997–Present Dept. of ECE, Professor |
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1993–1997 Dept. of ECE, Associate Professor |
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1988–1993 Dept. of ECE, Assistant Professor |
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Education |
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Ph.D. with honor, Computer
Engineering, The Center for Advanced Computer Studies, University of Louisiana, Lafayette, USA, June 1988. Dissertation
Title: Analysis of Cache-based Multiple-bus Multiprocessors. M.A.Sc., Dept. of Elec. Engin., B.Sc., Dept. of Computer Science,
Huazhong |
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Awards and honors |
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1. Outstanding Interlectual Property Award, University of Rhode Island. 2008 2. Faculty Excellence Award for Outstanding Entrepreneureship, University of Rhode Island, 2007; 3. Outstanding Interlectual Property Award, University of Rhode Island. 2007 4. Outstanding Interlectual Property Award, University of Rhode Island. 2005 5.
Aurelio Lucci Faculty Excellene Award, 2005,
for excellence in teaching, research and services, 1993, 6. Outstanding Interlectual Property Award, University of Rhode Island. 2001 7.
Distinguished Engineering Professor, 8.
NSF (National Science Foundation) Research
Initiation Award, RIA Award 1989 9.
Outstanding Young Man of 10.
Aurelio Lucci Faculty Excellene Award, 1993,
for excellence in teaching, research and services, 1993, 11.
Listed in "Who Is Who Among
Asian-Americans," 1993 and "Who Is Who in 12. 10 Best HUST alumni overseas 13. "A novel cache on data storage" A news article on Horizons, Spring 1999. 14.
"Yellow Crane Friendship Award" for
Outstanding work on scholar activities and technology transfers, 15. Cover story on International Talent Magzine June 2002, a national magzine published worldwide. 16. Keynote Speech at 2002 Shen Zhen HI-TECH Fair, Oct. 2002. 17. On the National News
of China, People's Daily (oversea's edition) |
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Note: 7 of the following patents have resulted in
license income to URI for over hundreds of thousands of dollars. 1.
“Prime-Mapped
Cache----A new cache memory system for vector processings,” US Patent
No. 5,379,393 Issued on 2.
“Disk
Caching Disk---A new architecture for high performance disk I/O systems,” US Patent and Trademark Office, PTO No.
5,754,888 3.
“RAPID-Cache
(Redundant, Asymmetrically Parallel, Inexpensive Disk Cache), A new cache
structure for RAID systems,'' U.S. Patent and Trademark Office, No.
6,243,795, 4.
“STICS--SCSI-To-IP
Cache Storage,” US Patent and Trademark Office, US Patent No. 7,275,134. (with Xubin He). 5.
“RORIB--A
cost effective approach for real-time, online and remote information
backup,'' US Patent No. 7,177,887. (with Jian Li). 6.
“HELP---Hardware
Environment for Low-overhead Profiling/Optimization and Security Functions,”
Provisional Patent Application Filed with US Patent and Trademark Office on 7.
“BUCS—Bottom
Up Cache Structure for networked storage servers,” Patent Application Filed with US Patent and
Trademark Office on 8.
“DRALIC---A webserver architecture based on
distributed RAID and location independence caching,'' File pending. (with Ben
(Xubin) He). 9.
“CEO-Cache,
A new cache architecture with low power consumption,” Filed 10.
“CUP:
Coupling Update by Parities, A method and apparatus for maximizing data
recovery," Application No. 60/940,831. 11.
“APS:
Method and Apparatus for Approximate Positioning System in Personal Area
Networks Using ZigBee" Application filed on March 28, 2006. 12.
“Methods for detecting unfair ratings and
building trust in raters in online rating systems using signal modeling
technique" Application Pending: 60/894,012 13.
“Coherent
and active/active redundant storages using sliding window of eager execution
transactions (SWEET)," US Patent Application Pending: 60/985,759. 14.
“Data
replication method over a limited bandwidth network by mirroring parities,"
U.S Patent pending and claims allowed: No. 11/017,436. 15. “Adaptive cache engine for storage area network including systems and methods related thereto," U.S. Patent pending, No. 11/054,933. 16. “TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time," US Patent pending, Application No. 60/883,181. 17. “RINGS: Recover Information from NAND Gates Storages”, US Patent and Trademark Office, Filed in May 2008. Co-inventor: Weijun Xiao |
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PUBLICATIONS
REFERENCED CONFERENCE PAPERS
9.
Ming Zhang, Yinan Liu, and Qing Yang,
"Cost-Effective Remote Mirroring Using the iSCSI Protocol", 21st IEEE
Conference on Mass Storage Systems and Technologies, April, 2004, pp.385-398.
10.
Ming Zhang, Qing Yang, and Xubin He, "SPEK: A
Storage Performance Evaluation Kernel Module for Block Level Storage
Systems", in Proceedings
of 11th IEEE/ACM
International Symposium on Modeling, Analysis, and Simulation of Computer and
Telecommunication Systems (MASCOTS), Orlando,
October 12-15, 2003.
11.
Ming Zhang, Xubin He, and Qing Yang, "A
Unified, Low-overhead Framework to Support Continuous Profiling and
Optimization", Proc. Of IEEE IPCCC 2003, Apr, 2003.
12.
Ming
Zhang and Qing Yang, "Evaluating
Availability of Networked Storages Using Commercial Workload", presented at Sixth Workshop on Computer Architecture
Evaluation using Commercial Workloads (CAECW), Feb, 2003.
13.
Ming
Zhang and Qing Yang, "N-SPEK: A Performability Benchmark Tool for
Networked Storage Systems", to be presented at Workshop on
Parallel I/O in Cluster Computing and Computational Grids., 12-15 May 2003,
Toshi Center Hotel, Tokyo, JAPAN
14.
Xubin
He, Qing Yang, and Ming Zhang, "A Caching
Strategy to Improve iSCSI Performance," in Proc. of
IEEE Annual Conference on Local Computer Networks, Nov. 6-8,2002.
15.
Xubin
He, Qing Yang, and Ming Zhang, "Introducing SCSI-To-IP
Cache for Storage Area Networks", IEEE International conference on
Parallel Processing (ICPP'2002),
August 2002, pp. 203-210.
16.
Ming
Zhang, Xubin He, and Qing Yang, "Implementation and Performance
Evaluation of RAPID-Cache under Linux,"
Proc. of the International Conference on Parallel and Distributed Processing
Techniques and Applications (PDPTA'2002), June 2002.
17.
Ming
Zhang and Xubin He, "A Unified, Low-overhead Framework to Support
Continuous Profiling and Optimization", to appear in Proceedings of
22nd IEEE International Performance Computing and Communications Conference
(IPCCC’2003),
18.
Xubin
He, Ming Zhang, and Qing Yang, "DRALIC: A Peer-to-Peer
Storage Architecture" Proceedings
of the International Conference on Parallel and Distributed Processing
Techniques and Applications (PDPTA'2001), Volume II, June 2001, pp. 908-913.
19.
Xubin
He and Qing Yang, "Characterizing the Home
Pages" Proceedings
of the 2nd International Conference on Internet Computing (IC’2001), June 2001, pp. 976-982.
20.
Xubin
He and Qing Yang, "VC-RAID: A Large Virtual
NVRAM Cache for Software Do-it-yourself RAID" Proceedings of the International
Symposium on Information Systems and Engineering (ISE'2001), June 2001, pp.334-340.
21.
Xubin
He and Qing Yang, "Performance evaluation of
distributed webservers under commercial workload" in Proceedings of Internet
Conference'2000,
22.
Xubin
He and Qing Yang, "A DCD Filter Driver for
Windows NT 4" Proceedings
of the 12th International Conference on Computer Applications in Industry and
Engineering
(CAINE-99),
23.
Yiming
Hu, Ashwini Nanda and Qing Yang, "Measurement, Analysis and Performance
Improvement of the Apache Web Server", in the 18th IEEE International
Performance, Computing and Communications Conference (IPCCC'99),
Phoenix/Scottsdale,
24.
T.
Nightingale, Y. Hu, and Qing Yang, “Design and Implementation of a DCD Device Driver for
Unix”, in Proceedings
of the 1999 USENIX Annual Technical Conference,
25.
Y.
Hu, Q. Yang, and T. Nightingale, ``RAPID-Cache --- A Reliable and Inexpensive
Write Cache for Disk I/O Systems", in the 5th International Symposium
on High Performance Computer Architecture (HPCA-5).
26.
Y.
Hu and Q. Yang, ``DCD---Disk Caching Disk: A New
Approach for Boosting I/O
Performance," 23rd Annual International Symposium on Computer
Architecture,
27.
H. Wang, T. Sun, and Q. Yang, ``Caching Address Tags: A
technique to reduce chip area cost for on-chip caches," 22nd Annual International
Symposium on Computer Architecture,Santa
28.
Q. Yang and Liping W. Yang, ``A novel cache design for vector
processing," Proc.
of 19th Int'l Symp. on Computer Architecture, May 1992, pp. 362-371.
29.
Li
Yang, X. Pei, and Qing Yang ``Performance Analysis of A new Disk Architecture
as A Netserver for NFS Network Systems", Int’l Conference on Computer Applications in Industry and Engineering (CAINE-96),
Dec. 1996.
30.
T. Sun and Q. Yang, ``Evaluating cache
performance for vector computers," In Proc.
Int’l Conf. on Parallel and Distributed
Computing, Oct. 1994.
31.
Chenyi
Hu, Baker Kearfott, Joe Sheldon and Qing
Yang, ``Solving nonlinear systems on
vector supercomputers," In Proc. Int'l
Conf. on Parallel and Distributed Computing, Oct. 1994.
32.
Sibabrata
Ray, Hong Jiang and Qing Yang, "A New Approach To Network Latency
Reduction of Multiprocessors by Data Migration in The Absence of Cache
Coherence Mechanisms" In Proc. ISCA
Int'l Conf. on Parallel and Distributed
Computing, Oct. 1994.
33.
N.
Annupindi, M. An, J. W. Cooley and Qing Yang, ``A new and efficient FFT
algorithm for distributed memory systems," in Proceedings of Internation Conference on Parallel and Distributed
Systems, Dec. 1994,
34.
T.
Sun and Q. Yang, ``A comparison of cached and uncached vector computers," in Proceedings of IEEE 1994 Int’l Conf. on Parallel and Distributed
Systems, Oct. 1994.
35.
Tao
Yang, Shengbin Hu and Qing Yang, ``A closed form formula for
queueing delays in diskarrays ," Proceedings of 94' Int'l Conf. on Parallel
Processing, Aug.
1994.
36.
Q.
Yang and S. Adina, ``A one's complement cache,"
Proceedings
of 94' Int'l Conf. on Parallel Processing, Aug. 1994.
37.
H.
Wang and Q. Yang, ``On fault tolerant computation of orthogonal transforms on
hypercube multiprocessors," In Proc.
of 21th Int'l Conf. on Parallel Processing, Vol. 1, Aug. 1992.
38.
Q.
Yang, ``Effects of arbitration protocols on the performance of multiple-bus
multiprocessors," In Proc. of 20th Int'l Conf. on Parallel Processing,
Vol. 1, 1991.
39.
H.
Wang and Q. Yang, ``A Prime-Cube graph approach for processor allocation in
hypercube multiprocessors," In Proc.
of 20th Int'l Conf. on Parallel Processing, Vol. 1, pp. 25-32, 1991.
40.
Qing
Yang and X. Qian, ``Load balancing on distributed multiprocessor architectures
with LAL", in Proc. on 11th Int,l
Conf. on Distributed Computing Systems, May 1991, pp. 402-409.
41.
C.
Hu, M. Bayoumi, B. Kearfott and Q. Yang, ``A parallelized algorithm for the
preconditioned interval
42.
Q.
Yang, G. Thangadurai and L. N. Bhuyan,
``An adaptive cache coherence scheme for hierarchical shared-memory
multiprocessors," IEEE Symp. on Parallel Processing, Dec.
1990.
43.
Qing
Yang and R. Ravi, ``Design and analysis
of multiple-bus arbiters with different priority schemes", in Proc. of PARBASE-90--Int. Conf. on Database,
Parallel Architectures, and Their
Applications, pp 238-247 March,
1990.
44.
Q.
Yang, ``On performance improvement of cache coherence protocols for
hierarchical multiprocessors," ISMM
Int'l Conf. on Parallel and Distributed
Computing, and Systems, Oct. 1990.
45.
Qing
Yang, ``Performance analysis of a cache coherent multiprocessor based on
hierarchical buses", in Proc. of
PARBASE-90--Int. Conf. on Database, Parallel Architectures, and Their
Applications, pp 248-257 March,
1990.
46.
Q.
Yang and L.N. Bhuyan, ``A queueing
network model for cache coherence protocol on asynchronous multiple-bus
multiprocessors," in 88'Int,l Conf. on Parallel Processing, pp.
130-137, 1988.
47.
Q.
Yang, L.N. Bhuyan, and R. Pavaskar,
``Performance analysis of packet switched multiple-bus multiprocessor
systems," in Proceedings of Eighth
Real-Time System Symposium, Dec. 1987, pp. 170-178.
48.
Q.
Yang and L.N. Bhuyan, ``Design and analysis of decentralized multiple-bus
multiprocessor," in Proceedings of
87'Int'l Conf. on Parallel Processing, Aug. 1987, pp. 889-892.
49.
Q.
Yang, D. Ghosal and L.N. Bhuyan, ``Analysis of Multiple Token-ring and Multiple
Slotted-ring Networks,'' IEEE Proceedings Computer Networking
Symposium,
50.
Q.
Yang, D. Ghosal and L.N. Bhuyan, “Design and analysis of multiple-ring networks
for distributed processing,” In TR
86-3-1, CACS, USL, 1986.
51.
Qing
Yang, D. Ghosal, and S. K. Tripathi, “Performance study of two protocols for
data/voice intergration on ring networks,”
UMIACS-TR-90-46,
52.
Yiming
Hu, Ashwini Nanda and Qing Yang,
“Profiling and performance enhancement of Appache web servers,” Tech.
Report, URI
JOURNAL
PAPERS
53. Jin Ren
and Qing Yang, “BLUVS: A Block Level Unlimited Versioning System,” Submitted to
IEEE Transaction on Computers.
54. Weijun
Xiao, Qing Yang, Jin Ren, Changsheng Xie, and Huaiyang Li, “Design and Analysis
of Block Level Snapshots for Data Protection and Recovery,” IEEE
Transaction on Computer, Under revision.
55. Weijun
Xiao, Jin Ren, and Qing Yang, “A Case for Continuous Data Protection at Block
Level in Disk Array Storages,” IEEE Transaction on Parallel and Distributed
Systems, To appear.
56. Weijun
Xiao, Yan Sun, Yinan Liu, and Qing Yang, “TEA: Transmission Error Approximation
for distance estimation between two Zigbee devices,” Int. J. High Performance
Computing and Networking, 2008,
to appear.
57. Xubin
He, Ming Zhang, and Qing Yang, "SPEK: A storage performance evaluation
kernel module for block level storage systems under faulty conditions" IEEE
Transaction on Dependable and Secture Computing , Vol. 2, No. 2, April-June
2005, pp. 138-149.
58. Xubin
He, Ming Zhang, and Qing Yang, "STICS:
SCSI-To-IP Cache for Storage Area Networks", Journal
of Parallel and Distributed Computing , vol. 64, No. 9, pp. 1069-1085,
September 2004.
59.
Scott
Lloyd, Jian Li, Joan Peckham, and Qing Yang, “RORIB, An economic and efficient
solution for Real-time, Online, Remote Information Backup,” in Journal of Database Management, JDM S00-294,
Vol. 14, No. 3, July-Sept. 2003, pp. 56-73.
60.
Y.
Hu, T. Nightingale and Q. Yang, ``RAPID-Cache --- A Reliable and
Inexpensive Write Cache for High Performance Storage Systems", IEEE Transactions on Parallel and
Distributed Systems,
Vol. 13, No. 3. March 2002, pp.290-307.
61.
Xubin
He and Qing Yang "Performance Evaluation of Distributed Web Server
Architectures under E-Commerce Workloads" Submitted to Journal of
Parallel and Distributed Computing.
62.
Xubin
He, Ming Zhang, and Qing Yang, "STICS: SCSI-To-IP Cache for Storage Area
Networks," Submitted to IEEE Transactions on Parallel and Distributed
Systems.
63.
Yiming
Hu, Ashwini Nanda and Qing Yang, "Measurement, Analysis and
Performance Improvement of the Apache Web Server", International Journal of Computers and
Their Applications, Vol. 8, No. 4,
Dec. 2001..
64.
Xubin
He and Qing Yang "On Design and
Implementation of a Large Virtual NVRAM Cache for Software RAID", in Special Issue of Calculateurs Parallel
Journal on Parallel I/O for Cluster Computing, 2002 spring.
65.
Y.
Hu and Q. Yang, `` A New Hierarchical Disk
Architecture", IEEE Micro,
Vol.
18, No. 6, Nov/Dec. 1998.
66.
T.
Sun and Q. Yang, ``A comparative analysis of cache
memories for vector processing," in IEEE Trans.
on Computers, Vol. 48, No.3 March 1999, pp. 331-344.
67.
Li
Yang, X. Pei, and Qing Yang ``Performance Analysis of A new Disk Architecture
as A Netserver for NFS Network Systems", in Int'l Journal on Computers and
Their Applications, Vol. 6, No. 3, Sept. 1999, pp. 159-165.
68.
H.
Wang, T. Sun, and Q. Yang, ``Minimizing area cost of on-chip
cache memories by caching address tags", In IEEE
Trans. on Computers, Vol. 46, No. 11. Nov. 1997, pp. 1187-1201.
69.
Q.
Yang, Sridah Adina and T. Sun, ``Designing on-chip cache using
complement numbers", in
Journal of Parallel and Distributed Computing, Academic Press. Vol. 48, pp.
143-164, 1998.
70.
Qing
Yang and Tao Yang, ``A memory interference model for
regularly patterned multiple stream vector accesses,''IEEE
Transactions on Parallel and Distributed Systems, Vol. 6, No. 5, pp. 520-530, May
1995.
71.
Qing
Yang, ``Introducing a new cache design into vector computers,'' in IEEE Transactions on Computers, Vol. 42,
No. 12, Dec. 1993, pp. 1411-1424. The Prime-mapped Cache
72.
Nagesh
Anupindi, Qing Yang and M. An, ``Tensor Product Formulations of Data Partition
and Migration for Matrix Transpose and FFT Algorithms", in Journal of Parallel and Distributed Computing.
73.
S.
Ray, H. Jiang and Q. Yang, ``A Compiler-directed Approach to Network Latency
Reduction in Distributed Shared Memory Multiprocessors", Journal of Parallel and Distributed
Computing, Special Issue on Compilation Techniques for Distributed Memory
Systems.
74.
C-M
Chung, D-A Chiang and Qing Yang ``A
comparative analysis of different
arbitration protocols for multiple-bus multiprocessors" International Journal of Computer Science
and Enigeering. Vol. 11, No. 3,May 1996.
75.
C.
Hu, A. Frolov, B. Kearfott, and Q. Yang, “A General Sparse Interval Linear
Solver and its Parallelization for the Interval
76.
C.
Hu, J. Sheldon, B. Kearfott, and Q. Yang, Optimizing INTBIS on the CRAY Y-MP, International Journal on Reliable Computing,
No. 3, 1995.
77.
Q.
Gan, Q. Yang and C. Y. Hu, ``Parallel all-row preconditioned interval linear
solver for nonlinear equations on multiprocessors,'' Parallel Computing, (20) 1994.
78.
Qing
Yang, ``Guest Editor's Introduction," in
IEEE Computer Society Tech. Comm.
on Comp. Arch. Newsletter, Special Issue on Cache Memories for
Supercomputers, Oct. 1993.
79.
Qing
Yang, ``Performance of cache memories for vector computers,'' in Journal of Parallel and Distributed Computing, Special Issue on
Performance of Supercomputers. 19 pp.163-178, 1993.
80.
Xiaoshu
Qian and Qing Yang, ``An analytical model for load balancing on symmetric
multiprocessor systems,'' in Journal of
Parallel and Distributed Computing, Vol. 20, 1994, pp. 198-211.
81.
Qing
Yang and H. Wang, ``A graph approach to
minimizing processor fragmentations on hypercube multiprocessors", in IEEE Transactions on Parallel and
Distributed Systems, Oct. 1993, pp. 1165-1171.
82.
Qing
Yang, D. Ghosal, and S. K. Tripathi, ``Performance study of two protocols for
voice/data integration on ring networks", in Computer Networks and ISDN Vol. 23, 1992, pp. 267-285.
83.
Qing
Yang, G. Thangadurai and L. N. Bhuyan,
``Design of a dynamic cache coherence scheme for large scale
multiprocessors", in IEEE
Transactions on Parallel and Distributed Systems, Vol. 3, No. 3, May 1992,
pp.281-293.
84.
Qing
Yang and L. N. Bhuyan, ``Analysis of Packet-Switched Multiple-Bus
Multiprocessor Systems,'' in IEEE
Transactions on Computers, Vol. 30, No. 3, March 1991, pp. 352-357.
85.
Qing
Yang and L. N. Bhuyan, ``Performance of Multiple-Bus Interconnections for
Multiprocessors,'' in Journal of Parallel
and Distributed Computing, 8. pp. 267-273 (1990).
86.
Qing
Yang, L. N. Bhuyan and B. Liu, ``Analysis and Comparison of Cache Coherence
Protocols for a Packet-Switched Multiprocessor,'' in IEEE Transactions on Computers,
Special Issue on Distributed Computer Systems, Aug. 1989, pp 1143-1153.
87.
L.
N. Bhuyan, D. Ghosal, and Qing Yang, ``Approximate Analysis of Single and
Multiple-ring Networks,'' in IEEE Transactions on Computers, July 1989,
pp 1027-1040.
88.
L.
N. Bhuyan, Qing Yang and D. P. Agrawal, ``Performance of Multiprocessor
Interconnection Networks", IEEE
Computer, vol. 22, No. 2, pp.25-37,
Feb. 1989.
89.
Qing
Yang and S. G. Zaky, ``Communication performance in multiple-bus systems",
IEEE Transactions on Computers, Vol.
32, No. 7, pp. 848-853, July 1988.
BOOK CHAPTERS
90.
Scott
J. Lloyd, Joan Peckham, Jian Li and Qing (Ken) Yang, "Simultaneous
Database Backup Using TCP/IP and Specialized Network Interface Card,"
Chapter IV, Advanced Topics in Database Research, Vol. 4, IGP: Idea Group
Publishing
91.
Xubin
He, Qing Yang, "A Large Virtual NVRAM Cache for Software RAID," Parallel
I/O for Cluster Computing (Chapter 7),
Editors: Christophe CÉRIN
and Hai JIN, 2002 September.
92.
Chapter
15: RAPID-Cache --- A Reliable and Inexpensive Write Cache for Disk I/O Systems
, in Hai Jin, Toni Cortes, and Rajkumar Buyya (editors), High Performance Mass
Storage and Parallel I/O: Technologies and Applications, IEEE & Wiley
Press, ISBN 0-471-20809-4, New York, USA, 2001.
93.
L.
N. Bhuyan, D. Ghosal, Q. Yang
``Approximate analysis of single and multiple ring networks", in Fiber Optic Local Area Networks, Ed:
Eric G. Rawson, SPIE Press, 1990.
94.
Qing
Yang, ``Performance analysis of a cache coherent multiprocessor based on
hierarchical buses", in Parallel
Architectures, Ed: N. Rishe, S. Navathe and D. Tal, IEEE Computer Society
Press, 1990.
95.
Qing
Yang and R. Ravi, ``Design and analysis
of multiple-bus arbiters with different priority schemes", in Parallel Architectures, Ed: N. Rishe,
S. Navathe and D. Tal, IEEE Computer Society Press, 1990.
96.
Qing
Yang, ``A conflict-free cache design ", in Practical Aspects of Parallel Computing, Ed: L. Tao, 1994.
97.
Qing
Yang, ``Processor allocation in multicomputers," in Practical Aspects of Parallel Computing, Ed: L. Tao, 1994.
98.
Qing
Yang, L. N. Bhuyan and B. Liu, ``Analysis and Comparison of Cache Coherence
Protocols for a Packet-Switched Multiprocessor,'' in
|
research grants and contracts |
|
|
1.
Qing
Yang, “Understanding, Analyzing, and Designing Storage Subsystem Architectures
for Maximum Data Recoverability,” National Science Foundation, Aug. 1, 2008 to
Aug. 1, 2011. Principal Investigator, 1 of 1.
2.
Qing
Yang, “Validation and Evaluation of a New Data Replication Technology,”
National Science Foundation, SGER Grant, Feb. 2006 to July 2007.
3.
Qing
Yang, “Design and Analysis of Data Processing and Storage in Image Processing
Systems,” NI, Aug. 1, 2007 to Sept. 2008. Principal Investigator, 1 of 1.
4.
Qing
Yang, "HELP - A Profiling Tool for Disk I/O and Networked Storage,"
National Science Foundation, CCR-0312613, ITR grant for $149,982, Aug. 2003 to
July 2006. Principal Investigator 1 of 1.
5.
Qing
Yang, "Boosting Webserver Performance Using DRALIC----Distributed RAID and
Location Independence Caching", National Science Foundation, 3 years for
$199,272, Sept. 2000 to Sept. 2003, Principal Investigator 1 of 1.
6.
Qing
Yang, ``A New Spectrum of Hierarchical Storage Architectures for High
Performance Disk I/Os." National Science Foundation, Grant No.
MIP-9714370. $359,466, (PI 1 of 1).
7.
Qing
Yang, ``Exploring desgin space for high performance low cost memory
hiearchy," National Science Foundation Grant No. MIP-9505601, Aug. 1995-Aug.
1998. $159,818, Principal Investigator (1 of 1).
8.
Qing
Yang, ``Introducing a new cache design into vector computers," National
Science Foundation Grant No. MIP-9208041, three years from June 1992 to Dec.
1995, $152,187, Principal Investigator (1 of 1).
9.
Qing
Yang, ``Design and analysis of high performance cache-coherent multiprocessors
based on shared buses", National Science Foundation grant CCR-8909672,
Aug. 1989 - July 1992., $60,000, Principal Investigator (Research Initiation
Award).
10.
"Equipment
for diverse computer architecture research" National Science Foundation,
Jan. 1998-Jan. 1999, $76,730, co-PI with Gus Uht, Don Tufts, J-C. Lo.
11.
Qing
Yang ``Effects of disk accesses on the performance of computer
systems",NSF, November 1996 - June 1997, $9,600.
12.
“Evaluating
Web Server performance on multiprocessors", IBM December 1996 --December
1997, $15,000.
13.
Qing
Yang ``Prototyping DCD", URI Research Council.
14.
Qing
Yang ``Research Experience for Undergraduates", National Science
Foundation, Aug. 1996 - July 1998. Principal Investigator.
15.
Qing
Yang,``Optimization of Parallel Computing on Cache-Coherent
Multiprocessor", Research Council Grant for July 1991-July 1992, Principal
Investigator.
16.
Travel
grant from National Science Foundation for to present a paper at ISCA92 in
17.
Qing
Yang, ``Innovative architecture designs for supercomputers," URI Research
Council for Aug. 1992 - Dec. 1992.,
Principal Investigator.
18.
Qing
Yang, ``Upgrading Computer Organization Lab," Intel Corp. April 1993,
Principal Investigator.
19.
Qing
Yang, United Nation Industrial Development Organization, UNIDO, Training In
ternational scholars May 1993.
20.
Qing
Yang, United Nation Industrial Development Organization, UNIDO, Training In
ternational scholars May 1994.
21.
Qing
Yang, ``Computer Applications in Industry," Xifeng Industrial Inc.
|
Graduate Students advised |
1.
Ph.D.
¯ Ming Zhang, May, 2005, Sr. Research Architect, Tandberg Co.
¯ Xubin Ben He, Ph.D,
July 2002,
Tenured Assoc. Professor, Department of Electrical and Computer Engineering,
¯ Yiming
Hu, Ph.D, Jan. 1999, Tenured Assoc. Prof. U. of Cincinnati,
winner of NSF 2000’ Career Award.
¯ Hong Wang, Ph.D,
Jan.
1996,
Intel Microprocessor Research Lab. Seniro Principal Researcher (Sr. Principal
Engineer), Intel Co. Winner of 1999 Intel Accomplishment Award.
¯ Nagesh Anupindi,
1994, Aware Inc,.
¯ Tong Sun, 1996,
Xerox Co. Senior Network Architect
2.
Master of
Science:
¯ Kurt R.
Almquist, George Thangadurai, Ravi Raja, Qi Gan, V. Geetha, J. Huang, Adina
Sridha, Kevin Yee, Gregory Bussiere, Jie Lu, Xiaosong He, Brian Capoccia, John
Didier, Jian Li, Yaodong Hu.
|
Professional Activities |
¯ Co-Founder and
Chair for IEEE International Conference on Networking, Architecture and
Storages. Successfully held for 3 consecutive years.
¯ Program
Committee Member: International Symposium on High Performance Computer
Architecture, 2006
¯ Program
Committee Member: IEEE International Symposium on Workload Characterization,
2005,
¯ Program
Committee Member: International Symposium on Computer Architecture and High
Performance Computing, 2005, SBAC-PAD05
¯ Program Committee
Member: IFIP International Conference on Network and Parallel Computing 2005
¯ Founder and Workshop
Chair, International Workshop on Storage Network Architecture and Parallel
I/Os, SNAPI’05. SNAPI has been successfully held annually for 4 years.
¯ Served in two
NSF Panels in 2005.
¯ Associate
Editor, IEEE Transaction on Parallel and Dsitributed Systems, 1999-2001.
¯ Membership
Chair, IEEE TCCA, 2002-present.
¯ Senior Member of
IEEE
¯ Distinguished
Speaker of IEEE Computer Society, 1996-1999.
¯ Program Committee
Chairman, Int’l Conf. On Computer Applications in Industry and Engineering,
Nov. 1999
¯ Program
Committee Chairman, International Workshop on High Performance Computing,
¯ Publication
Chairman, International Symposium on High Performance Computer Architecture
1995
¯ Program
Committee Members of several international conferences.
¯ Guest editor of
several professional journals.
¯ Invited speaker
for numerous universities and companies in the world.
¯ Referees for
several professional journals.
|
Personal information |
Married
with two daughters and two sons. Love badminton, tennis, and boating.