| 
   | 
  
 |
| 
   RESIT SENDAG Professor and Director of Graduate Studies,  Department of
  Electrical, Computer and Biomedical Engineering Facitelli
  Center for Advanced Engineering, Office: 403 2 East Alumni Avenue, Kingston, RI 02881 E-mail : sendag@uri.edu, Phone : (401)
  874-9423  | 
  
   
  | 
 
.
| 
   If you have questions
  about our graduate program, please refer to our AI-powered Graduate Program Chatbot. About: Resit Sendag is a Professor
  of Computer Engineering at the University of Rhode Island. He specializes in
  the broad area of computer architecture. His research interests include
  processor architecture; multicore processors; cache and memory hierarchies;
  memory scheduling techniques; non-volatile memories, instruction-set
  architecture (ISA); performance analysis and benchmarking; instruction-level
  (ILP), thread-level (TLP) and data-level parallelism (DLP); vector
  processing; hardware accelerator architectures; application-specific hardware
  design; energy-efficient design and processing; and high-performance
  computing. Research Assistantships Available. I am looking for highly motivated and
  hard-working students to work on various challenging projects in computer
  architecture. Requirements: Already received MSc degree; excellent skills in
  C++. Send me an email if interested.  | 
 
| 
   SELECTED RECENT PUBLICATIONS  | 
  
   · Maximilian Jakob Heer, José
  Quevedo, Marwan F. Abdelatti, Resit Sendag, Manbir
  Sodhi, Efficient Implementation of a Genetic Algorithm for the Capacitated
  Vehicle Routing Problem on a High-Performance FPGA. IEEE 31st Annual
  International Symposium on Field-Programmable Custom Computing Machines
  (FCCM’23). · José Quevedo, Maximilian Jakob
  Heer, Marwan F. Abdelatti, Resit Sendag, Manbir
  Sodhi, “Performance Comparison of Steady State GAs and Generational GAs for
  Capacitated Vehicle Routing Problems,” ACM Conference on Genetic
  and Evolutionary Computation, GECCO 2023. · Marwan Abdelatti,
  Manbir Sodhi and Resit Sendag, “A Multi-GPU Parallel Genetic Algorithm For Large-Scale Vehicle Routing Problems,” IEEE High
  Performance Extreme Computing Conference, Waltham, Massachusetts, Sep 19-23,
  2022. · Mustafa Cavus, Mohammed Shatnawi, Resit Sendag and Augustus Uht,
  “Fast Key-Value Lookups
  with Node Tracker,” ACM
  Transactions on Architecture and Code Optimization, Volume 18, Issue 3, June
  2021, pp 1-26. · Mustafa Cavus, Mohammed Shatnawi, Resit Sendag and Augustus Uht,
  “Exploring
  Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory
  Database Lookups. IEEE Computer Architecture Letters, 2020. · Mustafa Cavus, Resit Sendag and
  Joshua J Yi, “Informed
  Prefetching for Indirect Memory Accesses,” ACM Transactions on Architecture and Code Optimization, Volume 17,
  Issue 1, March 2020, pp 1-29. · Mustafa Cavus, Resit Sendag,
  Joshua J. Yi, “Array
  Tracking Prefetcher for Indirect Accesses,” IEEE International
  Conference on Computer Design (ICCD), Orlando, FL, USA, Oct 7-10, 2018. · Babak Falsafi,
  Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, Resit Sendag, “FPGAs
  versus GPUs in Data Centers,” IEEE Micro 37(1): 60-72 (2017). · Trevor N. Mudge,
  Frederic T. Chong, Igor L. Markov, Resit Sendag, Joshua J. Yi, Derek Chiou, “Impact of
  Future Technologies on Architecture,” IEEE
  Micro 36(4): 48-56 (2016).
    | 
 
| 
   PATENTS  | 
  
   · Cache
  Replacement Method, with Ayse Yilmazer and Augustus
  K. Uht, US Patent No. 7,721,048. · Branch
  Prediction Enhancement Method and Mechanism, US Patent No. 8,312,255.  | 
 
| 
   OPEN-SOURCE TOOLS  | 
  
   · PatternFinder
  - a generalized pattern analysis tool · z4800 – An Open-Source
  Multi-Core Platform on FPGA  | 
 
| 
   RECENT PROFESSIONAL ACTIVITIES  | 
  
   · Director,
  URI Computer Architecture Laboratory. · Director, URI Generative AI Development Group. · NSF Proposal Review Panelist,
  2006, 2007, 2011, 2013, 2016, 2017, 2018, 2022, 2023, 2024. · Program Committee Member,
  IEEE International Symposium on High
  Performance Computer Architecture (HPCA), 2023. · General Co-Chair,
  IEEE International Conference
  on Computer Design (ICCD), 2021. · General Co-Chair,
  BenchCouncil
  International Symposium on Benchmarking, Measuring and Optimizing (Bench),
  2021. · Program Committee Member,
  IEEE International Symposium on
  Workload Characterization (IISWC), 2021. · Program Chair,
  IEEE International
  Conference on Computer Design (ICCD), 2020. · Co-organizer, 5th Workshop on Computer Architecture
  Research Directions (CARD), Held in conjunction with the 46th International
  Symposium on Computer Architecture, June 2019, Phoenix, Arizona. Also
  co-organized CARD
  2007, CARD 2009, CARD 2011 and CARD 2015. · General
  Chair, 2016 IEEE International Symposium on
  Workload Characterization (IISWC), Oct 2016, Providence, Rhode Island,
  USA. · General
  Chair, 2015 IEEE International
  Conference on Networking, Architecture, and Storage (NAS), August 2015,
  Boston, MA, USA. · Program
  Committee Member,
  High Performance and Embedded Architecture and
  Compilation (HIPEAC 2019, 2018, 2017, 2016, 2015). · Program
  Committee Member, 2018 IEEE International
  Parallel and Distributed Computing Symposium (IPDPS 2018). · Publicity
  Chair, IEEE International Conference on
  Computer Design (ICCD 2018, 2017). · Steering
  Committee Member, IEEE International Symposium on Workload
  Characterization (IISWC), 2017-current. · Program
  Committee Member,
  IEEE International Conference
  on Computer Design 2016. · Program
  Committee Member,
  IEEE International Conference
  on Computer Design 2015. · ERC
  Member, ISCA 2022, MICRO 2022, HPCA 2022, ISCA 2021, HPCA 2021, ISCA 2020, MICRO 2020, HPCA 2020, HPCA 2019, ISCA 2017, HPCA 2017, MICRO 2016, ISCA 2016, HPCA 2016, HPCA 2015, ISCA 2015, MICRO 2015. · Distinguished
  Review Board Member,
  ACM Transactions on Architecture and Code
  Optimization, 2014-current. · Program
  Committee Member,
  2015 IEEE International
  Symposium on Workload Characterization (IISWC), Oct. 2015, Atlanta,
  Georgia.  | 
 
| 
   RECENT TEACHING  | 
  
   ·       ELE 208: Introduction to Computing Systems ·       ELE 305: Introduction to Computer Architecture ·       EGR 404: Developing Tools with Generative AI ·       ELE 548: Graduate Computer Architecture  | 
 
| 
   STUDENT ADVISING  (out of date)  | 
  
   Current
  Graduate Students (Thesis) Advised ·    
  Jonathan Pollard ·    
  Justin Watkins Generative AI Development Group ·    
  Justin Watkins, Jack Demarinis, Richard
  Buckley, Garrett Kemper, Zack Notarianni. Former
  Graduated Students (Thesis Advised) ·    
  Maximilian Heer, graduated with MSc.
  2022, Now PhD student at ETH-Zurich. ·    
  Travis Frink, graduated with MSc. 2022,
  Now at Taco Comfort Solutions Inc, RI.  ·    
  Matthew Constant, graduated with MSc.
  2020, Now at AMD, MA. ·    
  Mustafa Cavus, graduated with PhD. 2019,
  Now at Intel, OR. ·    
  Herman Hoffmann, graduated with MSc.
  2017, Now at US Army Reserve Command,
  NC. ·    
  Peter Morley, graduated with MSc. 2017.
  Now at NVIDIA, MA. ·    
  Celal Ozturk, graduated with PhD., 2013
  Now at Intel, OR. ·    
  Andre Zierfuss,
  graduated with MSc., 2013. Now at Volkswagen
  Research Lab, CA.  ·    
  Ronald Duarte, graduated with MSc., 2013
  Now at MIT Lincoln Labs, MA. ·    
  Will Simoneau, graduated with MSc.,
  2011. Now at Naval Undersea Warfare
  Center, RI. ·    
  Ayse Yilmazer,
  graduated with M.Sc., Now Professor at Istanbul technical University.  | 
 
| 
   | 
  
   |