4 East Alumni Ave., Kingston, RI 02881
Email: sendag At ele DOT uri . edu
Office: Kelley Annex A-219
Phone: (401) 874-9423 Fax: (401) 782-6422
Resit Sendag joined University of Rhode Island in November 2003 and is currently a Professor of Electrical, Computer and Biomedical Engineering. Dr. Sendag received his Ph.D. degree from University of Minnesota-Twin Cities, Minneapolis, MN, USA, in Electrical Engineering, in 2003. His research interests include multi-core architectures; power/performance issues for high-performance and embedded computer systems; and performance evaluation and simulation techniques.
Research Assistantships Available. I am looking for highly-motivated and hard-working students to work on various challenging projects in computer architecture. Requirements: Already received MSc degree; excellent skills in C++. Send me an email if interested.
Selected Recent Publications
· Mustafa Cavus, Resit Sendag, Joshua J. Yi, “Informed Prefetching for Indirect Memory Accesses,” ACM Transactions on Code Optimizations, 2019.pdf
· Mustafa Cavus, Resit Sendag, Joshua J. Yi, “Array Tracking Prefetcher for Indirect Accesses,” IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, Oct 7-10, 2018.pdf
· Babak Falsafi, Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, Resit Sendag, “FPGAs versus GPUs in Data Centers,” IEEE Micro 37(1): 60-72 (2017). pdf
· Trevor N. Mudge, Frederic T. Chong, Igor L. Markov, Resit Sendag, Joshua J. Yi, Derek Chiou, “Impact of Future Technologies on Architecture,” IEEE Micro 36(4): 48-56 (2016).pdf
· Mark D. Hill, Dave Christie, David A. Patterson, Joshua J. Yi, Derek Chiou, Resit Sendag, “Proprietary versus Open Instruction Sets,” IEEE Micro 36(4): 58-68 (2016). pdf
· Mustafa Cavus, Ibrahim Karsli and Resit Sendag, “Prefetching on-time and When it works,” 2nd Data Prefetching Championship, in conjunction with ISCA-41, Portland, OR, June 2015. 3rd Place.pdf
· Cache Replacement Method, with Ayse Yilmazer and Augustus K. Uht, Issued 2010. US Patent No. 7,721,048.
· Branch Prediction Enhancement Method and Mechanism, Issued 2012. US Patent No. 8,312,255.
· z4800 – An Open Source Multi-Core Platform on FPGA – available for download.
· Director, URI Microarchitecture Research Insights Laboratory.
· General Chair, 2016 IEEE International Symposium on Workload Characterization (IISWC), Oct 2016, Providence, Rhode Island, USA.
· General Chair, 2015 IEEE International Conference on Networking, Architecture, and Storage (NAS), August 2015, Boston, MA, USA.
· Program Committee Member, High Performance and Embedded Architecture and Compilation (HIPEAC 2019, 2018, 2017, 2016, 2015).
· Program Committee Member, 2018 IEEE International Parallel and Distributed Computing Symposium (IPDPS 2018).
· Publicity Chair, IEEE International Conference on Computer Design (ICCD 2018, 2017).
· Steering Committee Member, IEEE International Symposium on Workload Characterization (IISWC), 2017.
· Steering Committee Member, IEEE International Conference on Networking, Architecture, and Storage (NAS), 2016.
· Program Committee Member, IEEE International Conference on Computer Design (ICCD 2016, 2015).
· Co-organizer, 4th Workshop on Computer Architecture Research Directions (CARD), Held in conjunction with the 42nd International Symposium on Computer Architecture, June 2015, Portland, Oregon.
· Distinguished Review Board Member, ACM Transactions on Architecture and Code Optimization, 2014-current.
· Program Committee Member, 2015 IEEE International Symposium on Workload Characterization (IISWC), Oct. 2015, Atlanta, Georgia.
· NSF Proposal Review Panelist, (2006-current).
· ELE 305 Introduction to Computer Architecture
· ELE 405 Digital Computer Design
· ELE 548 Computer Architecture
· ELE 648 Advanced Topics in Computer Architecture