1999 IEEE North Atlantic Test Workshop

Final Program

Thursday, May 27, 1999

[7:30am - 8:00am] Breakfast & Registration

[8:00am - 9:10am] Opening Session

Keynote Speech: "The Challenges of Testing Future Mixed Signal Products," Samuel Fuller, VP R&D, Analog Devices Inc.

[9:20am - 10:50am] Session 1: Verification and Functional Test Chair: F. Lombardi, Northeastern Univ.

  1. Functional Redesign by Genetic Identification, L. Ngom, C. Baron and J.-C. Geffroy, INSA-TLSE, France
  2. Application of a TTCN Based Protocal Integrated Testing System on the Transmission Control Protocal, X. Yin and J. Wu, Tsinghua Univ., P.R.C.
  3. Automated Test Data Generation for Architecture Validation of a Processor's Instruction Set, A. Manogar, M. M. Babu, S. Nanda and V. P. Haneefa, Software and Silicon Systems, India
[11:00am - 12:30pm] Session 2: Test Generation Chair: T. Chakraborty, Bell Labs. Lucent
  1. A Successful Effort in Improving the Efficiency of Weighted Random Pattern Test System,  P. Chang, B. Keller and D. Pruden, IBM
  2. Flush Testing of Pipeline Partial Scan Strutures - An Industrial Experiment,   X. Chen, T. Snethen, J. Swenton and R. Walther, IBM
  3. An Automatic Test Generation Algorithm for Functional Testing at Register Transfer Language Level, S. Su, SUNY-Binghampton

[12:30pm - 1:30pm] Lunch

[1:30pm - 6:30pm] Excursion to Newport, RI

[6:30pm - 7:30pm] Dinner

[7:30pm - 9:30pm] Panel Session Manufacturing Systems on Silicon (SOC) Containing Mixed Signal Components

Moderator: J. Monzel, IBM

Panelists: E. S. Cooley, Dartmouth College, B. Kaminska, OPMaxx, A. Righter, Analog Devices Inc., R. Bulaga, IBM

Friday, May 28, 1999

[7:30am - 8:20am] Breakfast & Registration

[8:20am - 9:50am] Session 3: Defect and Failure Analysis Chair: L. Huisman, IBM

  1. The Clustering Effect on Defect Level Modeling,   J. T. de Sousa, Bell Labs.
  2. Diagnosing Interconnects of Random Access Memories, J. Zhao, F. J. Meyer and F. Lombardi, Northeastern Univ.
  3. An Improved Paradigm of Certainty Theory to Solve the Uncertainty Problem in System Diagnosis,   C. Liang, H. Zhao and W. Shi, Chinese Academy of Sciences
  4. High Resolution Diagnostic Techniques for the IBM S/390 Microprocessor,   P. Song, F. Motika, M. Kusko, R. Rizzolo, J. Lee and R. Clairmont, IBM
[10:00am - 12:00pm] Session 4: Testing of Cores and System-on-Silicon Chair: R. Davies, Compaq Computer
  1. Test Access Architecture for System-on-a-Chip Designs,   K. Chakrabarty, Duke Univ.
  2. Standard for testing Cores, Are We on the Right Boat?.   S. Bhawmik and S. Wu, Bell Labs, Lucent
  3. Testing Complex System on a Chip ASIC Products Incorporating Video DACs,   B. Cowan, J. Monzel, M. Styduhar, R. Bulaga and L. Brooks, IBM
  4. An Observability Register Architecture for Efficient Production Test and Debug, D. Bhavsar and R. Tan, Compaq Computer Corp.
[12:00pm - 1:00pm] Lunch

[1:00pm - 3:00pm] Session 5: BIST and DFT Chair: K. Chakrabarty, Duke Univ.

  1. Reconvergent Fanout Removal Through Partial BIST Insertion,   I. G. Harris, Univ. Mass. At Amherst
  2. Built In Self test of a Quad DCVS ALU: A Case Study,   E. S. Cooley and R. K. Grube, Dartmouth College
  3. The Power Bus Stability Problem in Built-In Current Sensor Designs,   Y.-Y. Guo and J.-C. Lo, Univ. Rhode Island
  4. Design and Implementation of a Parallel Weighted Random Pattern and Logic Built In Self Test,   P. Chang, B. Keller and S. Paliwal, IBM