*

Research Interests

Professional Activities

Book Chapters

Refereed Publications

Technical Reports

Work experience

Patent Applications

Honors and Awards

Memberships

Links

 

 

RESEARCH

INTERESTS
  • High-performance computer architecture; including parallel processing, multi-core processors, memory systems, computer systems performance analysis, and mathematical modeling
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PATENTS
  • Cache Replacement Method, with Ayse Yilmazer and Augustus K. Uht, Issued 2010. US Patent No. 7,721,048.
  • Branch Prediction Enhancement Method and Mechanism, Issued 2012. US Patent No. 8,312,255.
  • Storing Execution Results of Mispredicted Paths in a Superscalar Computer Processsor, with David J. Lilja and Steven R. Kunkel (Patent pending).

 

 

 

 

 

BOOK

CHAPTERS
  • Joshua J. Yi, Resit Sendag, and David J. Lilja, “Instruction Precomputation: Dynamically Removing Redundant Computations Using Profiling,” Chapter 10 in Speculative Execution in Modern Computer Architectures, edited by Pen-Chung Yew and David Kaeli, CRC Press, 2005. ISBN 1-58488-447-9. pdf
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REFEREED

PUBLICATIONS
  • Ronald Duarte, Resit Sendag and Fred Vetter, "On the performance and energy-efficiency of multi-core SIMD CPUs and CUDA-enabled GPUs," IEEE International Symposium on Workload Characterization, Portland, Oregon, Sep 2013.pdf
  • Ronald Duarte and Resit Sendag, "Accelerating and Characterizing Seam Carving Using a Heterogeneous CPU-GPU System," 12th International Conference on Parallel and Distributed Processing Techniques and Applications, July 2012.pdf
  • Will Simoneau and Resit Sendag, "An FPGA-based Multi-Core Platform for Testing and Analysis of Architectural Techniques," IEEE Symposium on Performance Analysis of Systems and Software (ISPASS), April 2012, New Brunswick, NJ.pdf
  • Ronald Duarte and Resit Sendag, "Real-time Video and Image Resizing using CUDA-Enabled GPUs," 3rd Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-3), in conjunction with the International Symposium on High Performance Computer Architecture (HPCA-18), February 2012, New Orleans, Louisiana.pdf
  • Peng-fei Chuang, Celal Ozturk, Khun Ban, Huijun Yan, Kingsum Chow, and Resit Sendag, "Impact of Java Application Server Evolution on Computer System Performance," Workshop on Modeling, Benchmarking and Simulation (MOBS), in conjunction with the International Symposium in Computer Architecture (ISCA), June 2011.pdf
  • James C. Hoe, Doug Burger, Joel Emer, Derek Chiou, Resit Sendag, Joshua Yi, "The Future of Architectural Simulation," IEEE Micro, pp. 8-18, May/June, 2010. pdf
  • Arvind , David August, Keshav Pingali, Derek Chiou, Resit Sendag, Joshua J. Yi, "Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?," IEEE Micro, pp. 19-33, May/June, 2010. pdf
  • Celal Ozturk, Resit Sendag, “An Analysis of Hard to Predict Branches,” IEEE Symposium on Performance Analysis of Systems and Software (ISPASS-2010), March 2010, White Plains, NY. pdf
  • Sharookh Daruwalla, Resit Sendag and Joshua J. Yi, “Adaptive simulation sampling using an Autoregressive framework,” IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, July 2009. pdf
  • Resit Sendag, Joshua Yi, Peng-fei Chuang, and David J. Lilja “Low Power/Area Branch Prediction Using Complementary Branch Predictors,” IEEE International Parallel and Distributed Processing Symposium, April 2008.pdf
  • Resit Sendag, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, “The Impact of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems,” Journal of Parallel and Distributed Computing, Special Issue on Best Papers in IEEE International Parallel and Distributed Processing Symposium, vol. 67, no. 12, pp. 1256-1269, Dec., 2007. pdf
  • Joel Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag, "Single-Threaded vs. Multithreaded: Where Should We Focus?," IEEE MICRO , vol. 27, no. 6,  pp. 14-24, November/December, 2007.pdf
  • Shay Gueron, Jean-Pierre Seifert, Geoffrey Strongin, Derek Chiou, Resit Sendag, Joshua J. Yi, "Where Does Security Stand? New Vulnerabilities vs. Trusted Computing," IEEE MICRO, vol. 27, no. 6,  pp. 25-35, November/December, 2007.pdf
  • Antonio González, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi, "Reliability: Fallacy or Reality?," IEEE MICRO , vol. 27, no. 6,  pp. 36-45, November/December, 2007.pdf
  • Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou, "Low-Power Design and Temperature Management," IEEE MICRO, vol. 27, no. 6,  pp. 46-57, November/December, 2007.pdf
  • Joshua J. Yi, Resit Sendag, David J. Lilja, Douglas M. Hawkins, "Speed versus Accuracy Trade-Offs in Microarchitectural Simulations," IEEE Transactions on Computers, vol. 56,  no. 11,  pp. 1549-1563,  Nov.,  2007. pdf
  • Resit Sendag, Joshua Yi, and Peng-fei Chuang, “Branch Misprediction Prediction: Complementary Branch Predictors,” IEEE Computer Architecture Letters, Sept. 2007. pdf
  • Ayse Yilmazer, Resit Sendag, and Joshua J. Yi, “Quantifying and Comparing the Impact of Wrong-Path Memory References in Multiple-CMP Systems,” CMP-MSI: Workshop on Chip Multiprocessor Memory Systems and Interconnects, in conjunction with the 13th Annual International Conference on High-Performance Architecture (HPCA-13), February 2007. pdf
  • Resit Sendag, Joshua J. Yi, and Peng-fei Chuang, “Predicting When a Branch Predictor Will Fail,” Boston Area Computer Architecture Workshop, January 2007.
  • Joshua J. Yi, Resit Sendag, Lieven Eeckhout,  Ajay Joshi, David J. Lilja, and Lizy K John, " Evaluating Benchmark Subsetting Approaches,” IEEE International Symposium on Workload Characterization, October 2006. pdf
  • Emre Ozer, Resit Sendag, David Gregg, “Multiple-Valued Logic Buses for Reducing Bus Energy in Low-power Systems,” IEE Computers and Digital Techniques, Volume 153, no 4, pp. 270-282, July 2006. pdf
  • Resit Sendag, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, "Quantifying and Reducing the Effects of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems," IEEE International Parallel and Distributed Processing Symposium, April 2006. Best Paper Award Winner! (out of 531 papers submitted.) pdf
  • Ayse Yilmazer, Resit Sendag, Joshua J. Yi, and Augustus K. Uht, "Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems," Boston Area Computer Architecture Workshop, February 2006. pdf
  • Joshua J. Yi, Ajay Joshi, Resit Sendag, Lieven Eeckhout, and David J. Lilja, "Analyzing the Processor Bottlenecks in SPEC CPU 2000," SPEC Benchmark Workshop, January 2006. Kaivalya Dixit Award for the Best Paper! pdf
  • Emre Ozer, Resit Sendag, and David Gregg, “Multiple-Valued Logic Buses for Reducing Bus Size, Transitions and Power in Deep Submicron Technologies,” Advanced Networking and Communications Hardware Workshop (ANCHOR), in conjunction with International Symposium on Computer Architecture (ISCA-32), June 2005. pdf
  • Emre Ozer, Resit Sendag, and David Gregg, “Multiple-Valued Caches for Power-Efficient Embedded Systems”, IEEE International Symposium on Multiple-Valued Logic (ISMVL-35), May 2005. pdf
  • Resit Sendag, Ying Chen and David J. Lilja, “The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture”, IEEE Transactions on Parallel and Distributed Systems, Volume 16, No. 3, pp. 271-285, March 2005. pdf
  • Joshua J. Yi, Sreekumar Kodakara, Resit Sendag, David J. Lilja, and Douglas M. Hawkins, Characterizing and Comparing Prevailing Simulation Techniques, IEEE International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 266-277, Feb. 2005. pdf
  • Peng-fei Chuang, Resit Sendag, and David J. Lilja, “Improving Data Cache Performance via Address Correlation: An Upper Bound Study,” ACM Euro-Par 2004, Lecture Notes in Computer Science, vol. 3149/2004, pp. 541-550, Sep. 2004. pdf
  • Resit Sendag, Pengfei Chuang, and David J Lilja, “Address Correlation,” Boston Area Architecture Workshop (BARC 2004), Jan. 2004.
  • Resit Sendag, Pengfei Chuang, and David J Lilja, “Address Correlation: Exceeding the limits of Locality,” IEEE Computer Architecture Letters, Volume 2, May 2003. pdf
  • Ying Chen, Resit Sendag, and David J. Lilja, “Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor,” in Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS 2003), April 2003. pdf
  • Keqiang Wu, Resit Sendag, and David J. Lilja, “Exploring the Memory Access Regularity in Pointer-Intensive Application programs,” 4th International Conference on Intelligent Data Engineering and Automated Learning, Lecture Notes in Computer Science, vol. 2690/2003, pp. 472-476. March 2003. pdf
  • Resit Sendag, Ying, Chen and David J Lilja, “The Effect of Executing Mispredicted Load Instructions on Speculative Multithreaded Architecture,” 6th Workshop on Multi-threaded Execution, Architecture and Compilation, held in conjunction with IEEE MICRO-35, November 2002, pp. 19-26. pdf
  • Resit Sendag, David J Lilja, and Steven R Kunkel, “Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions,” ACM Euro-Par 2002, Lecture Notes in Computer Science, vol. 2400/2002, pp. 468-480. pdf
  • Joshua J. Yi, Resit Sendag, and David J. Lilja, “Increasing Instruction-Level Parallelism with Instruction Precomputation” ACM Euro-Par 2002, Lecture Notes in Computer Science, vol. 2400/2002, pp. 481-485. pdf
  • Resit Sendag; Peng-fei Chuang, and David H.C. Du, “Routing and Wavelength Assignment in Optical Passive Star Networks with Non-uniform Traffic Load,” IEEE GLOBECOM '01, Volume: 3, 2001 pp. 1435 –1439. pdf
  • Resit Sendag and A. Hamit Serbest., “Scattering at the Junction Formed by a PEC Half-Plane and a Half-Plane with Anisotropic Conductivity,” Electromagnetics, the Journal of, Volume: 21, No: 5, 2001 pp. 415-435. pdf
  • Resit Sendag and A. Hamit Serbest,  “Scattering of Plane Electromagnetic Waves at the Junction Formed by a PEC Half-Plane and a Half-Plane with Anisotropic Conductivity,” IEEE MELECON 98, 9th, Volume: 1, 1998 pp. 278 -282. pdf
  • Resit Sendag, Michael A. Lyalinov and A. Hamit Serbest, “Perturbation Method in the Problem of Diffraction of an Obliquely Incident Plane Wave by a Wedge with Different Surface Impedances,” URSI'98 Electromagnetic Theory Symposium, Thesaloniki, Greece, May 1998.

 

 

PAPERS

Under Review
  • Peng-fei Chuang, Shruti Patil, Resit Sendag, Joshua J Yi, and David J Lilja, “Avoiding Statistical Pitfalls in Interpreting Sampled Microarchitecture Simulation Results,” submitted for publication.
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TECHNICAL

REPORTS
  • Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, and Douglas M. Hawkins, "Characterizing and Comparing Prevailing Simulation Techniques," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 04-06, November 2004.
  • Keqiang  Wu,  Resit Sendag, and  David J. Lilja, Using a Self-tuning Adaptive Predictor to Characterize the Regularity of Memory Accesses in Pointer-Intensive Application Programs , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 03-03, March, 2003.
  • Resit Sendag, Ying Chen, and David J. Lilja, The Effect of Executing Mispredicted Load Instructions in a Speculative Multithreaded Architecture , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 02-11, November, 2002.
  • Joshua J. Yi, Resit Sendag, and David J. Lilja, The Spatial Characteristics of Load Instructions , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 02-10, October, 2002.
  • Ying Chen, Resit Sendag, and David J. Lilja, Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 02-09, October, 2002.
  • Resit Sendag, David J. Lilja, and Steven R. Kunkel, Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 02-05, May, 2002.
  • Joshua J. Yi, Resit Sendag, and David J. Lilja, Increasing Instruction-Level Parallelism with Instruction Precomputation , Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 02-01, February, 2002.
  • Resit Sendag; Peng-fei Chuang, and David H.C. Du, Design Issues on WTDM Optical Passive Star Networks, Computer Science Dept., University of Minnesota, November 2000
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RESEARCH and

WORK

EXPERIENCE
  • Department of Electrical, Computer and Biomedical Engineering, University of Rhode Island, Kingston, RI

Associate Professor

2009 to present

 
  • Department of Electrical, Computer and Biomedical Engineering, University of Rhode Island, Kingston, RI

Assistant Professor

2004 to 2009

 
  • Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

Research Assistant

2000 to 2004
    • Performed research on several data prefetching, speculative execution and value reuse/prediction techniques for uniprocessor and multiprocessor systems
    • Developed two techniques to hide the latency for memory accesses in superscalar and multithreaded processor architectures: Incorrect Speculation and Address Correlation

 
  • IBM Corporation, Future Processor Performance, Server Group, Rochester, MN

Intern

Summer 2001
    • Assisted with the evaluation of memory nest performance and the improvement of cache coherency protocol for xSeries and zSeries IBM Server systems.
    • Implemented next-line prefetching mechanism and developed a new cache coherency model using the cache simulator for xSeries and zSeries systems

 
  • Department of Electrical and Electronics Engineering, Cukurova University, Adana, Turkey

Research Assistant

1995 to 1998
    • Conducted Research on the development of Wiener-Hopf Factorization method and Maliuzhinetz’s technique for the vectorial Electromagnetic diffraction problems and their applications in computations of electromagnetic fields in complex structures: diffraction by coated, anisotropic or chiral surfaces and wedges

 

 

 

 

PROFESSIONAL

ACTIVITIES
  • Co-director, URI Microarchitecture Research Insights Laboratory, Jan 2004-present
  • NSF Panelist, National Science Foundation Proposal Review Panel, May 2013.
  • Program Committee Member, 27th IEEE International Parallel & Distributed Processing Symposium, IPDPS 2013, May 2013, Boston, MA.
  • Program Committee Member, 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-21), September 2012, Minneapolis, Minnesota.
  • Visiting Professor, supported by TUBITAK 2221 program, TOBB  University, Turkey, June 2012.
  • Program Committee Member, 7th International Workshop on Unique Chips and Systems (UCAS-7) held in conjunction with the 18th International Symposium on High-Performance Computer Architecture (HPCA-18) in New Orleans, Louisiana, February 26, 2012.
  • Publicity Chair, 18th International Symposium on High-Performance Computer Architecture (HPCA-18), February 2012, New Orleans, Louisiana.
  • NSF Panelist, National Science Foundation Proposal Review Panel, June 2011.
  • Co-organizer, 3rd Workshop on Computer Architecture Research Directions (CARD), Held in conjunction with the 38th International Symposium on Computer Architecture (ISCA-38), June 2011. http://www.ele.uri.edu/CARD.
  • Publications Chair, 38th International Symposium on Computer Architecture (ISCA-38), June 2011, San Jose, CA.
  • Program Committee Member, 6th IEEE International Conference on Networking, Architecture, and Storage (NAS) 2011.
  • Program Committee Member, 6th International Workshop on Unique Chips and Systems (UCAS-6) held in conjunction with the 43rd IEEE/ACM International Symposium on Microarchitecture (Micro-43) in Atlanta, USA, December 4, 2010
  • Session Chair, IEEE ISPASS-2010, March 2010, White Plains, NY.
  • Registration Chair, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2010), March 2010, White Plains, NY.
  • Program Committee Member, 5th IEEE International Conference on Networking, Architecture, and Storage (NAS) 2010.
  • Publications Chair, IEEE International Symposium on Workload Characterization (IISWC), October 2009, Austin Texas.
  • Co-organizer, Workshop on Computer Architecture Research Directions (CARD), Held in conjunction with the 36th International Symposium on Computer Architecture (ISCA-36), June 2009. http://www.ele.uri.edu/CARD.
  • Program Committee Member, 4th IEEE International Conference on Networking, Architecture, and Storage (NAS) 2009.
  • Program Committee Member, SPEC Benchmark Workshop 2009.
  • NSF Proposal Panelist, National Science Foundation, 2007.
  • Local Arrangements Chair, IEEE International Symposium on Workload Characterization, IISWC 2007, October 2007.
  • NSF Proposal Panelist, National Science Foundation, 2006.
  • Co-organizer (with Joshua Yi and Derek Chiou), Workshop on Computer Architecture Research Directions (CARD-2007), Held in Conjunction with the International Symposium on High-Performance Computer Architecture (HPCA-13), February 2007. About 5000 Video downloads since March 2007!
  • Program Committee Member, 5th Boston Area Computer Architecture Workshop, BARC 2007, January 2007.
  • Program Committee Member, Workshop on Modeling, Benchmarking and Simulation (MoBS), Held in Conjunction with the International Symposium on Computer Architecture (ISCA-33), June 2006.
  • Co-organizer and Co-chair (with Gus Uht), 4th Boston Area Computer Architecture Workshop, BARC 2006, Feb 2006.
  • Program Committee Member, 4th Boston Area Computer Architecture Workshop, BARC 2006, Feb 2006
  • Session Chair, Workshop on Modeling, Benchmarking and Simulation (MoBS), Held in Conjunction with the International Symposium on Computer Architecture (ISCA-32), June 2005.
  • Program Committee Member, IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005.
  • Reviewed numerous conference (ISCA, HPCA, MICRO, PACT, Euro-Par, ICPP, etc.) and journal (IEEE Trans. on Computers, IEEE Trans. on Parallel and Distr. Systems, Journal of Parallel and Distr. Computing, etc.) papers.
  • Designed a new course, Introduction to Computing Systems, 2005, which was recently added to the Computer Engineering Curriculum at the University of Rhode Island (URI).
  • Organizer, bi-weekly High-Performance Computing Seminar, University of Rhode Island.
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HONORS and

AWARDS
  • URI Recognition Award for Outstanding Contributions to Intellectual Property, 2013.
  • CARD 2009 Workshop featured in a special issue of IEEE MICRO May/June, 2010.
  • CARD 2007 Workshop featured in a special issue of IEEE MICRO Nov/Dec, 2007.
  • URI Recognition Award for outstanding contributions to Intellectual Property, 2007.
  • Best Paper Award winner (out of 531 papers submitted) at the IEEE International Parallel and Distributed Processing Symposium (IPDPS 2006), 24% acceptance rate.
  • Kaivalya Dixit Award (in memory of long-time President of Standard Performance Evaluation Corporation) for the Best Paper (the most useful contribution to industry and academia) at SPEC Benchmark Workshop 2006.
  • Scholarship from Ministry of Education of Turkey to pursue PhD degree at a university abroad (1999-2000).
  • Conference Travel Award, IEEE MICRO 35 Conference, 2002.
  • Minnesota Supercomputing Institute Travel Award, Euro-Par 2002 Conference, 2002.
  • NATO ASI (Advanced Study Institute) scholarship 1997.
  • NATO ASI scholarship, 1996.
  • The Scientific and Technological Research Council of Turkey Travel Award, 1996
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MEMBERSHIPS
  • Member, Institute of Electrical and Electronics Engineers (IEEE)
  • Member, IEEE Computer Society
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LINKS