Description
|
Documentation
|
Download
|
Inverter
|
inv_50.pdf
|
inv_50.mag
|
And gate
|
and_50.pdf
|
and_50.mag
|
Or gate
|
or_50.pdf
|
or_50.mag
|
Nand gates
|
nand_50.pdf
|
nand_50.mag,
nand3_50.mag
nand4_50.mag,
nand5_50.mag
|
Full Adder
|
1badd1_50.pdf
|
1badd1_50.mag,
8brcadd1_50.mag
|
Full Adder
(Transmission gate)
|
tgadd1_50.pdf
|
tgadd1_50.mag,
8btgadd1_50.mag
8btgadd2_50.mag
|
Full Adder (Transmission gate
with Outputs Buffered)
|
tgadd2_50.pdf
|
tgadd1_50.mag
|
Dynamic D Flip-Flop
|
dff2_50.pdf
|
dff2_50.mag
|
Dynamic T Flip-Flop
|
tff3_50.pdf
|
tff3_50.mag
|
Dynamic T FF with Enable
|
tff4_50.pdf
|
tff4_50.mag
|
Dynamic T FF with Reset
|
tff5_50.pdf
|
tff5_50.mag
|
Dynamic T FF with Reset and
Enable
|
tff6_50.pdf
|
tff6_50.mag
|
Static T Flip-Flop with Reset
|
stff1_50.pdf
|
stff1_50.mag
|
Dynamic Asynchronous Counter
|
ascntr1_50.pdf
|
ascntr1_50.mag
|
Static Asynchronous Counter
|
ascntr2_50.pdf
|
ascntr2_50.mag
|
Dynamic Synchronous Counter
|
scntr1_50.pdf
|
scntr1_50.mag
|
Static Synchronous Counter
|
scntr2_50.pdf
|
scntr2_50.mag
|
2-1 Multiplexer
|
mux2to1_50.pdf
|
mux2to1_50.mag
|
2-1 Complimentary Multiplexer
|
mux2to1c_50.pdf
|
mux2to1c_50.mag
|
4-1 Multiplexer
|
mux4to1_50.pdf
|
mux4to1_50.mag
|
